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microcomputer system requirements for event counting, interrupt and
interval timing, and general clock rate generation.
System design is simplified by connecting the CTC directly to both the
Z80 CPU and the Z80 SIO with no additional logic. In larger systems,
address decoders and buffers may be required.
The CTC allows easy programming: each channel is programmed with
two bytes; a third is necessary when interrupts are enabled. When started,
the CTC counts down, automatically reloads its lime constant, and
resumes counting. Software timing loops are eliminated. Interrupt
processing is simplified because only one vector needs to be specified; the
CTC internally generates a unique vector for each channel.
The Z80 CTC requires a single +5V power supply and the standard Z80
single-phase system clock. It is packaged in 28-pin DIPs, a 44-pin plastic
chip carrier, and a 44-pin Quad Flat Pack. The QFP package is only
available for CMOS versions.
The internal structure of the Z80 CTC consists of:
• A Z80 CPU bus interface, internal control logic
• Four sets of Counter/Timer Channel logic
• Interrupt control logic
The four independent, counter/timer channels are identified by sequential
numbers from 0 to 3. The CTC can generate a unique interrupt vector for
each separate channel for automatic vectoring to an interrupt service
www.DataSrohuteineet.4TUhe.cfooumr channels can be connected in four contiguous slots in the
standard Z80 priority chain with channel number 0 having the highest