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Z80 Family CPU Peripherals
User Manual
UM008101-0601
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UM008101-0601
Disclaimer
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Z80 CPU Peripherals User Manual
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Table of Contents
Counter/Timer Channels
CTC Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 CTC General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 CTC Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Structure of Channel Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Interrupt Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 CTC Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 CTC Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 CTC Counter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 CTC Timer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 CTC Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Loading The Channel Control Register . . . . . . . . . . . . . . . . . . . .19 Loading The Time Constant Register . . . . . . . . . . . . . . . . . . . . . .22 Loading The Interrupt Vector Register . . . . . . . . . . . . . . . . . . . . .22 CTC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 CTC Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 CTC Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 CTC Counting and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 CTC Interrupt Servicing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Interrupt Acknowledge Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 www.DataSheet4U.com Return from Interrupt Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Daisy-Chain Interrupt Servicing . . . . . . . . . . . . . . . . . . . . . . . . . .30
UM008101-0601 Table of Contents
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Direct Memory Access
DMA Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 CPU Data Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 DMA Data Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 DMA Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 DMA Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.