Document
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ZILOG
MICROPROCESSOR
PRODUCT SPECIFICATION
Z380™
MICROPROCESSOR
FEATURES
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Static CMOS Design with Low-Power Standby Mode Option 32-Bit Internal Data Paths and ALU
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Two-Clock Cycle Instruction Execution Minimum Four Banks of On-Chip Register Files Enhanced Interrupt Capabilities, Including 16-Bit Vector Undefined Opcode Trap for Z380™ Instruction Set On-Chip I/O Functions: - Six-Memory Chip Selects with Programmable Waits - Programmable I/O Waits - DRAM Refresh Controller 100-Pin QFP Package
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Operating Frequency - DC-to-18 MHz at 5V - DC-to-10 MHz at 3.3V Enhanced Instruction Set that Maintains Object-Code Compatibility with Z80® and Z180™ Microprocessors 16-Bit (64K) or 32-Bit (4G) Linear Address Space 16-Bit Data Bus with Dynamic Sizing
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GENERAL DESCRIPTION
The Z380™ Microprocessor is an integrated highperformance microprocessor with fast and efficient throughput and increased memory addressing capabilities. The Z380™ offers a continuing growth path for present Z80-or Z180-based designs, while maintaining Z80® CPU and Z180® MPU object-code compatibility. The Z380™ MPU enhancements include an improved 280 CPU, expanded 4-Gbyte space and flexible bus interface timing. An enhanced version of the Z80 CPU is key to the Z380 MPU. The basic addressing modes of the Z80 microprocessor have been augmented as follows: Stack Pointer Relative loads and stores, 16-bit and 24-bit indexed offsets, and more flexible Indirect Register addressing, with all of the addressing modes allowing access to the entire 32-bit address space. Additions made to the instruction set, include a full complement of 16-bit arithmetic and logical operations, 16-bit I/O operations, multiply and divide, plus a complete set of register-to-register loads and exchanges. The expanded basic register file of the Z80 MPU microprocessor includes alternate register versions of the IX and IY registers. There are four sets of this basic Z80 microprocessor register file present in the Z380 MPU, along with the necessary resources to manage switching between the different register sets. All of the register-pairs and index registers in the basic Z80 microprocessor register file are expanded to 32 bits.
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ZILOG
MICROPROCESSOR
GENERAL DESCRIPTION (Continued)
The Z380 MPU expands the basic 64 Kbyte Z80 and Z180 address space to a full 4 Gbyte (32-bit) address space. This address space is linear and completely accessible to the user program. The I/O address space is similarly expanded to a full 4 Gbyte (32-bit) range and 16-bit I/O, and both simple and block move are added. Some features that have traditionally been handled by external peripheral devices have been incorporated in the design of the Z380 microprocessor. The on-chip peripherals reduce system chip count and reduce interconnection on the external bus. The Z380 MPU contains a refresh controller for DRAMs that employs a /CAS-before-/RAS refresh cycle at a programmable rate and burst size. Six programmable memory-chip selects are available, along with programmable wait-state generators for each chip-select address range. The Z380 MPU provides flexible bus interface timing, with separate control signals and timing for memory and I/O. The memory bus control signals provide timing references suitable for direct interface to DRAM, static RAM, EPROM, or ROM. Full control of the memory bus timing is possible because the /WAIT signal is sampled three times during a memory transaction, allowing complete user control of edge-to-edge timing between the reference signals provided by the Z380 MPU. The I/O bus control signals allow direct interface to members of the Z80 family of peripherals, the Z8000 family of peripherals, or the Z8500 series of peripherals. Figure 1 shows the Z380 block diagram; Figure 2 shows the pin assignments.
Note:
All signals with a preceding front slash, "/", are active Low e.g., B//W (WORD is active Low); B/W is active Low, only)
Power connections follow conventional descriptions below:
Connection Power Ground
Circuit VCC GND
Device VDD VSS
Clock with Standby Control Chip Selects and Waits Refresh Control
External Interface Logic
Interrupts
CPU
Data (16) Address (32)
/EV VDD VSS
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Figure 1. Z380 Functional Block Diagram
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ZILOG
MICROPROCESSOR
A5 A4 A3 A2 A1 A0 VSS VDD VSS VDD /TREFR /TREFA /TREFC /BHEN /BLEN /MRD /MWR /MSIZE /WAIT BUSCLK IOCLK /M1 /IORQ /IORD CLKI CLKO /IOWR VSS VDD VSS
1
2
100
95
90
85
80
A23 A24 A25 A26
5 75
A27 A28 A29 A30
10 70
A31 VSS VDD VSS D0
15
Z380 100-Pin QFP
65
D1 D2 D3 D4 D5 D6 D7 60 D8 D9 D10 D11 D12 55 D13 D14
D15 VDD
20
25
30
35
40
45
50
VSS
Figure 2. 100-Pin QFP Pin Assignments
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ZILOG
MICROPROCESSOR
PIN DESCRIPTION
A31-A0 Address Bus (outputs, active High, tri-state). These non-multiplexed address sig.