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P80C32. P-80C32 Datasheet

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P80C32. P-80C32 Datasheet







P-80C32 P80C32. Datasheet pdf. Equivalent




P-80C32 P80C32. Datasheet pdf. Equivalent





Part

P-80C32

Description

P80C32

Manufacture

ETC

Datasheet
Download P-80C32 Datasheet


ETC P-80C32

P-80C32; www.DataSheet4U.com 80C32/80C52 CMOS 0 to 44 MHz Single Chip 8–bit Microntro ller Description TEMIC’s 80C52 and 80 C32 are high performance CMOS versions of the 8052/8032 NMOS single chip 8 bit µC. The fully static design of the TE MIC 80C52/80C32 allows to reduce system power consumption by bringing the cloc k frequency down to any value, even DC, without loss of data. .


ETC P-80C32

The 80C52 retains all the features of th e 8052 : 8 K bytes of ROM ; 256 bytes o f RAM ; 32 I/O lines ; three 16 bit tim ers ; a 6-source, 2-level interrupt str ucture ; a full duplex serial port ; an d on-chip oscillator and clock circuits . In addition, the 80C52 has 2 software -selectable modes of reduced activity f or further reduction in power consumpti on. In the idle mo.


ETC P-80C32

de the CPU is frozen while the RAM, the timers, the serial port and the interru pt system continue to function. In the power down mode the RAM is saved and al l other functions are inoperative. The 80C32 is identical to the 80C52 except that it has no on-chip ROM. TEMIC’s 8 0C52/80C32 are manufactured using SCMOS process which allows them to run from 0 up to 44 MHz with .



Part

P-80C32

Description

P80C32

Manufacture

ETC

Datasheet
Download P-80C32 Datasheet




 P-80C32
www.DataSheet4U.com
80C32/80C52
CMOS 0 to 44 MHz Single Chip 8–bit Microntroller
Description
TEMIC’s 80C52 and 80C32 are high performance CMOS
versions of the 8052/8032 NMOS single chip 8 bit µC.
The fully static design of the TEMIC 80C52/80C32
allows to reduce system power consumption by bringing
the clock frequency down to any value, even DC, without
loss of data.
The 80C52 retains all the features of the 8052 : 8 K bytes
of ROM ; 256 bytes of RAM ; 32 I/O lines ; three 16 bit
timers ; a 6-source, 2-level interrupt structure ; a full
duplex serial port ; and on-chip oscillator and clock
circuits. In addition, the 80C52 has 2 software-selectable
modes of reduced activity for further reduction in power
consumption. In the idle mode the CPU is frozen while
the RAM, the timers, the serial port and the interrupt
system continue to function. In the power down mode the
RAM is saved and all other functions are inoperative.
The 80C32 is identical to the 80C52 except that it has no
on-chip ROM. TEMIC’s 80C52/80C32 are manufactured
using SCMOS process which allows them to run from 0
up to 44 MHz with Vcc = 5 V.
TEMIC’s 80C52 and 80C32 are also available at 16 MHz
with 2.7 V < VCC < 5.5 V.
D 80C32 : Romless version of the 80C52
D 80C32/80C52-L16 : Low power version
Vcc : 2.7 – 5.5 V Freq : 0-16 MHz
D 80C32/80C52-12 : 0 to 12 MHz
D 80C32/80C52-16 : 0 to 16 MHz
D 80C32/80C52-20 : 0 to 20 MHz
D 80C32/80C52-25 : 0 to 25 MHz
D 80C32/80C52-30 : 0 to 30 MHz
D 80C32/80C52-36 : 0 to 36 MHz
D 80C32-40 : 0 to 40 MHz*
D 80C32-42 : 0 to 42 MHz*
D 80C32-44 : 0 to 44 MHz*
* 0 to 70°C temperature range.
For other speed and temperature range availability please consult your
sales office.
Features
D Power control modes
D 256 bytes of RAM
D 8 Kbytes of ROM (80C52)
D 32 programmable I/O lines
D Three 16 bit timer/counters
D 64 K program memory space
D 64 K data memory space
D Fully static design
D 0.8µ CMOS process
D Boolean processor
D 6 interrupt sources
D Programmable serial port
D Temperature range : commercial, industrial, automotive,
military
Optional
D Secret ROM : Encryption
D Secret TAG : Identification number
MATRA MHS
Rev. G (14 Jan. 97)
1





 P-80C32
www.DataSheet4U.com
80C32/80C52
Interface
Figure 1. Block Diagram
2 MATRA MHS
Rev. G (14 Jan. 97)





 P-80C32
www.DataSheet4U.com
Figure 2. Pin Configuration
80C32/80C52
P1.5
P1.6
P1.7
RST
RxD/P3.0
NC
TxD/P3.1
INT0/P3.2
INT1/P3.3
T0/P3.4
T1/P3.5
80C32/80C52
P0.4/A4
P0.5/A5
P0.6/A6
P0.7/A7
EA
NC
ALE
PSEN
P2.7/A14
P2.6/A13
P2.5/A12
DIL
P15
P16
P17
RST
RxD/P30
NC
TxD/P31
INT0/P32
INT1/P33
T0/P34
T1/P35
LCC
80C32/80C52
P04 /A4
P05 /A5
P06 /A6
P07 /A7
EA
NC
ALE
PSEN
P27 /A15
P26 /A14
P25 /A13
Flat Pack
Diagrams are for reference only. Package sizes are not to scale.
MATRA MHS
Rev. G (14 Jan. 97)
3



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