Document
www.DataSheet4U.com
80C32/80C52
CMOS 0 to 44 MHz Single Chip 8–bit Microntroller
Description
TEMIC’s 80C52 and 80C32 are high performance CMOS versions of the 8052/8032 NMOS single chip 8 bit µC. The fully static design of the TEMIC 80C52/80C32 allows to reduce system power consumption by bringing the clock frequency down to any value, even DC, without loss of data. The 80C52 retains all the features of the 8052 : 8 K bytes of ROM ; 256 bytes of RAM ; 32 I/O lines ; three 16 bit timers ; a 6-source, 2-level interrupt structure ; a full duplex serial port ; and on-chip oscillator and clock circuits. In addition, the 80C52 has 2 software-selectable modes of reduced activity for further reduction in power consumption. In the idle mode the CPU is frozen while the RAM, the timers, the serial port and the interrupt system continue to function. In the power down mode the RAM is saved and all other functions are inoperative. The 80C32 is identical to the 80C52 except that it has no on-chip ROM. TEMIC’s 80C52/80C32 are manufactured using SCMOS process which allows them to run from 0 up to 44 MHz with Vcc = 5 V. TEMIC’s 80C52 and 80C32 are also available at 16 MHz with 2.7 V < VCC < 5.5 V.
D D D D
D 80C32 : Romless version of the 80C52 D 80C32/80C52-L16 : Low power version Vcc : 2.7 – 5.5 V Freq : 0-16 MHz D 80C32/80C52-12 : 0 to 12 MHz D 80C32/80C52-16 : 0 to 16 MHz D 80C32/80C52-20 : 0 to 20 MHz D 80C32/80C52-25 : 0 to 25 MHz D 80C32/80C52-30 : 0 to 30 MHz
80C32/80C52-36 : 0 to 36 MHz 80C32-40 : 0 to 40 MHz* 80C32-42 : 0 to 42 MHz* 80C32-44 : 0 to 44 MHz*
* 0 to 70°C temperature range. For other speed and temperature range availability please consult your sales office.
Features
D D D D D D D Power control modes 256 bytes of RAM 8 Kbytes of ROM (80C52) 32 programmable I/O lines Three 16 bit timer/counters 64 K program memory space 64 K data memory space D D D D D D Fully static design 0.8µ CMOS process Boolean processor 6 interrupt sources Programmable serial port Temperature range : commercial, industrial, automotive, military
Optional
D Secret ROM : Encryption D Secret TAG : Identification number
MATRA MHS Rev. G (14 Jan. 97)
1
www.DataSheet4U.com
80C32/80C52
Interface
Figure 1. Block Diagram
2
MATRA MHS Rev. G (14 Jan. 97)
www.DataSheet4U.com
80C32/80C52
Figure 2. Pin Configuration
P1.1/T2EX
P0.0/A0
P0.1/A1
P0.2/A2
P1.5 P1.6 P1.7 RST RxD/P3.0 NC TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5
P0.3/A3
P1.0/T2
VCC
P1.4
P1.3
P1.2
NC
P0.4/A4 P0.5/A5 P0.6/A6 P0.7/A7 EA
80C32/80C52
NC ALE PSEN P2.7/A14 P2.6/A13 P2.5/A12
DIL
P11 /T2EX P10 /T2 A1/P01 A2/P02 A3/P03 A0/P00 P14 P13 P12 NC VCC
LCC
P15 P16 P17 RST RxD/P30 NC TxD/P31 INT0/P32 INT1/P33 T0/P34 T1/P35
P04 /A4 P05 /A5 P06 /A6 P07 /A7 EA
80C32/80C52
NC ALE PSEN P27 /A15 P26 /A14 P25 /A13
WR/P36
RD/P37
P23 /A11
P20 /A8
P21 /A9
P22 /A10
Flat Pack
Diagrams are for reference only. Package sizes are not to scale.
P24 /A12
XTAL2
XTAL1
V SS
NC
P2.3/A10
P2.4/A11
P2.0/A7
P2.1/A8
WR/P3.6
RD/P3.7
P2.2/A9
XTAL2
XTAL1
VSS
NC
MATRA MHS Rev. G (14 Jan. 97)
3
www.DataSheet4U.com
80C32/80C52
Pin Description
VSS
Circuit ground potential. Memory that use 16 bit addresses (MOVX @DPTR). In this application, it uses strong internal pullups when emitting 1’s. During accesses to external Data Memory that use 8 bit addresses (MOVX @Ri), Port 2 emits the contents of the P2 Special Function Register. It also receives the high-order address bits and control signals during program verification in the 80C52. Port 2 can sink/source three LS TTL inputs. It can drive CMOS inputs without external pullups.
VCC
Supply voltage during normal, Idle, and Power Down operation.
Port 0
Port 0 is an 8 bit open drain bi-directional I/O port. Port 0 pins that have 1’s written to them float, and in that state can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external Program and Data Memory. In this application it uses strong internal pullups when emitting 1’s. Port 0 also outputs the code bytes during program verification in the 80C52. External pullups are required during program verification. Port 0 can sink eight LS TTL inputs.
Port 3
Port 3 is an 8 bit bi-directional I/O port with internal pullups. Port 3 pins that have 1’s written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (ILL, on the data sheet) because of the pullups. It also serves the functions of various special features of the TEMIC 51 Family, as listed below.
Port Pin
P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7
Alternate Function
RXD (serial input port) TXD (serial output port) INT0 (external interrupt 0) INT1 (external interrupt 1) TD (Timer 0 external input) T1 (Timer 1 external input) WR (external Data Memory write strobe) RD (external Data Memory read strobe)
Port 1
Port 1 is an 8 bit bi-dire.