3.3V Zero Delay Buffer
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September 2005 rev 1.4
ASM5P23S08A
3.3V ‘SpreadTrak’ Zero Delay Buffer
General Features
• • • • Z...
Description
www.DataSheet4U.com
September 2005 rev 1.4
ASM5P23S08A
3.3V ‘SpreadTrak’ Zero Delay Buffer
General Features
Zero input - output propagation delay, adjustable by capacitive load on FBK input. Multiple configurations Refer “ASM5P23S08A Configurations” Table. Input frequency range: 15MHz to 133MHz Multiple low-skew outputs. o Output-output skew less than 200pS. o Device-device skew less than 700pS. o Two banks of four outputs, three-stateable by two select inputs. Less than 200pS Cycle-to-cycle jitter (-1, -1H, -2, -3, -4, -5H). Available in 16 pin SOIC and TSSOP Packages. 3.3V operation. Advanced 0.35µ CMOS technology. Industrial temperature available. ‘SpreadTrak’. The ASM5P23S08A has two banks of four outputs each, which can be controlled by the select inputs as shown in the Select Input Decoding Table. The select input also allows the input clock to be directly applied to the outputs for chip and system testing purposes. Multiple ASM5P23S08A devices can accept the same input clock and distribute it. In this case the skew between the outputs of the two devices is guaranteed to be less than 700pS. The ASM5P23S08A (Refer is available in five different
configurations
“ASM5P23S08A
Configurations
Table). The ASM5P23S08A-1 is the base part, where the output frequencies equal the reference if there is no counter in the feedback path. The ASM5P23S08A-1H is the high-drive version of the -1 and the rise and fall times on this device are faster. The ASM5P23S08...
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