Communications MicroController. HPC36400E Datasheet

HPC36400E MicroController. Datasheet pdf. Equivalent

HPC36400E Datasheet
Recommendation HPC36400E Datasheet
Part HPC36400E
Description (HPC36400E / HPC46400E) High-Performance Communications MicroController
Feature HPC36400E; www.DataSheet4U.com HPC36400E HPC46400E High-Performance Communications MicroController PRELIMINAR.
Manufacture National Semiconductor
Datasheet
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National Semiconductor HPC36400E
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PRELIMINARY
November 1992
HPC36400E HPC46400E
High-Performance Communications MicroController
General Description
The HPC46400E is an upgraded HPC16400 Features have
been added to support V 120 the 8-bit mode has been en-
hanced to support all instructions and the UART has been
changed to provide more flexibility and power The
HPC46400E is fully upward compatible with the HPC16400
The HPC46400E has 4 functional blocks to support a wide
range of communication application-2 HDLC channels 4
channel DMA controller to facilitate data flow for the HDLC
channels programmable serial interface and UART
The serial interface decoder allows the 2 HDLC channels to
be used with devices using interchip serial link for point-to-
point and multipoint data exchanges The decoder gener-
ates enable signals for the HDLC channels allowing multi-
plexed D and B channel data to be accessed
The HDLC channels manage the link by providing sequenc-
ing using the HDLC framing along with error control based
upon a cyclic redundancy check (CRC) Multiple address
recognition modes and both bit and byte modes of opera-
tion are supported
The HPC36400E and HPC46400E are available in 68-pin
PLCC and 80-pin PQFP packages
Features
Y HPCTM family core features
16-bit data bus ALU and registers
64 kbytes of external memory addressing
FAST 20 0 MHz system clock
Four 16-bit timer counters with WATCHDOGTM logic
MICROWIRE PLUSTM serial I O interface
CMOS low power with two power save modes
Y Two full duplex HDLC channels
Optimized for ISDN X 25 V 120 and LAPD
applications
Programmable frame address recognition
Up to 4 65 Mbps serial data rate
Built in diagnostics
Synchronous bypass mode
Optional CRC generation
Received CRC bytes can be read by the CPU
Y Four channel DMA controller
Y 8- or 16-bit external data bus
Y UART
Full duplex
7 8 or 9 data bits
Even odd mark space or no parity
7 8 1 or 2 stop bit generation
Accurate internal baud rate generation up to 625k
baud without penalty of using expensive crystal
Synchronous and asynchronous modes of operation
Y Serial Decoder
Supports 6 popular time division multiplexing proto-
cols for inter-chip communications
Optional rate adaptation of 64 kbit s data rate to
56 kbit s
Y Over Mbyte of extended addressing
Y Easy interface to National’s DASL ‘U’ and ‘S’ trans-
ceivers TP3400 TP3410 and TP3420
Y Commercial (0 C to a70 C) and industrial (b40 C to
a85 C)
Block Diagram
TapePak and TRI-STATE are registered trademarks of National Semiconductor Corporation
HPCTM MICROWIRE PLUSTM and WATCHDOGTM are trademarks of National Semiconductor Corporation
IBM PC-AT are registered trademarks of International Business Machines Corporation
Sun is a registered trademark of Sun Microsystems
SunOSTM is a trademark of Sun Microsystems
UNIX is a registered trademark of AT T Bell Laboratories
C1995 National Semiconductor Corporation TL DD10422
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TL DD 10422 – 1
RRD-B30M115 Printed in U S A



National Semiconductor HPC36400E
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Absolute Maximum Ratings
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Total Allowable Source or Sink Current
100 mA
Storage Temperature Range
b65 C to a150 C
Lead Temperature (Soldering 10 sec )
300 C
VCC with Respect to GND
b0 5V to 7 0V
All Other Pins
(VCC a 0 5)V to (GND b 0 5)V
Note Absolute maximum ratings indicate limits beyond
which damage to the device may occur DC and AC electri-
cal specifications are not ensured when operating the de-
vice at absolute maximum ratings
DC Electrical Characteristics VCC e 5 0V g10% unless otherwise specified TA e 0 C to a70 C for
HPC46400E b40 C to a85 C for HPC36400E
Symbol
Parameter
Test Conditions
Min Max Units
ICC1
Supply Current
VCC e 5 5V fin e 20 0 MHz (Note 1)
VCC e 5 5V fin e 2 0 MHz (Note 1)
ICC2
IDLE Mode Current
VCC e 5 5V fin e 20 0 MHz (Note 1)
VCC e 5 5V fin e 2 0 MHz (Note 1)
ICC3
HALT Mode Current
VCC e 5 5V fin e 0 kHz (Note 1)
VCC e 2 5V fin e 0 kHz (Note 1)
INPUT VOLTAGE LEVELS SCHMITT TRIGGERED RESET WO D0 NMI I2 I3 AND ALSO CKI
VIH1
VIL1
Logic High
Logic Low
0 9 VCC
INPUT VOLTAGE LEVELS PORT A
VIH2
VIL2
Logic High
Logic Low
20
INPUT VOLTAGE LEVELS ALL OTHERS
VIH3
VIL3
Logic High
Logic Low
0 7 VCC
ILI Input Leakage Current
(Note 2)
CI Input Capacitance
(Note 3)
CIO I O Capacitance
(Note 3)
OUTPUT VOLTAGE LEVELS
VOH1
VOL1
VOH2
VOL2
VOH3
VOL3
VOH4
VOL4
Logic High (CMOS)
Logic Low (CMOS)
Port A B Drive CK2
(A0 – A15 B10 B11 B12 B15)
Other Port Pin Drive WO (open drain)
(B0 – B9 B13 B14 R0 – R7 D5 D7)
ST1 and ST2 Drive
IOH e b10 mA (Note 3)
IOL e 10 mA (Note 3)
IOH e b1 mA
IOL e 3 mA
IOH e b1 6 mA (except WO)
IOL e 0 5 mA
IOH e b6 mA
IOL e 1 6 mA (Note 4)
VCC b 0 1
24
24
24
VRAM
RAM Keep-Alive Voltage
(Note 5)
25
IOZ TRI-STATE Leakage Current
VIN e 0 and VIN e VCC
70
10
10
2
500
150
0 1 VCC
08
0 2 VCC
g1
10
20
01
04
04
04
g5
mA
mA
mA
mA
mA
mA
V
V
V
V
V
V
mA
pF
pF
V
V
V
V
V
V
V
V
V
mA
Note 1 ICC1 ICC2 ICC3 measured with no external drive (IOH and IOL e 0 IIH and IIL e 0) ICC1 is measured with RESET e VSS ICC3 is measured with NMI e
VCC CKI driven to VIH1 and VIL1 with rise and fall times less than 10 ns
Note 2 RDY HLD and RDY I4 pins have internal pullups and meet this spec only at VIN e VCC
Note 3 These parameters are guaranteed by design and are not tested
Note 4 ST2 drive will not meet this spec under condition of RESET pin e low
Note 5 Test duration is 100 ms
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National Semiconductor HPC36400E
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AC Electrical Characteristics
(see Notes 1 and 4 and Figures 1 thru 5 ) VCC e 5V g10% TA e 0 C to a70 C for HPC46400E b40 C to a85 C for
HPC36400E
Symbol and Formula
fC
tC1 e 1 fC
tCKIH
tCKIL
tC e 2 fC
tWAIT e tC
tDC1C2R
tDC1C2F
fU e fC 8
fMW
tHCK e 4tC1 a 14
fXIN e fC 22
Parameter and Notes
Operating Frequency
Operating Period
CKI Rise Time
CKI Fall Time
CPU or DMA Timing Cycle
CPU or DMA Wait State Period
Delay of CK2 Rising Edge after
CKI Falling Edge
Delay of CK2 Falling Edge after
CKI Falling Edge
External UART Clock Input Frequency
External MICROWIRE PLUS
Clock Input Frequency
HDLC Clock Input Period
External Timer Input Frequency
Min
2
50
22 5
22 5
100
100
0
Max
20
500
55
Units
MHz
ns
ns
ns
ns
ns
ns
Note
(Note 2)
0 55 ns (Note 2)
2 5 MHz
1 25 MHz
214
0 91
ns
kHz
tXIN e tC
Pulse Width for Timer Inputs
100 ns
tUWS
MICROWIRE Setup Time Master
Slave
100
20
ns
ns
tUWH
MICROWIRE Hold Time Master
Slave
20
50
ns
ns
tUWV
MICROWIRE Output Valid Time Master
Slave
50 ns
150 ns
tSALE e tC a 40
HLD Falling Edge before ALE Rising Edge
115
ns
tHWP e tC a 35
HLD Pulse Width
110 ns
tHAE e tC a 100
HLDA Falling Edge after HLD Falling Edge
175 ns (Note 3)
tHAD e tC a 85
HLDA Rising Edge after HLD Rising Edge
210 ns
tBF Bus Float after HLDA Falling Edge
66 ns
tBE e tC b 66
Bus Enable after HLDA Rising Edge
34
ns
Note 1 These AC characteristics are guaranteed with external clock drive on CKI having 50% duty cycle and with less than 15 pF load on CKO Spec’d tC1R tC1F
and CKI duty cycle limits are not tested but are guaranteed functional by design Keep in mind that when SLOW mode is selected fC (Operating Frequency) will be
the external frequency divided by 4 and that value should be used in all formulas relating to the AC Characteristics
Note 2 Do not design with this parameter unless CKI is driven with an active signal and SLOW mode is not selected When using a passive crystal circuit its
stability is not guaranteed if either CKI or CKO is connected to any external logic other than the passive components of the crystal circuit
Note 3 tHAE is spec’d for case with HLD falling edge occurring at the latest time it can be accepted during the present CPU or DMA cycle being executed If HLD
falling edge occurs later tHAE as long as (3 tC a 4 WS a 72 tC a 100) may occur depending on the following CPU instruction or DMA cycle its wait states and
ready input
Note 4 WS (tWAIT) c (number of preprogrammed wait states) Minimum and maximum values are calculated at maximum operating frequency fC e 20 MHz with
one wait state preprogrammed These values are guaranteed with AC loading of 100 pF on Port A 50 pF on CK2 80 pF on other outputs and DC loading of the
pin’s DC spec non CMOS IOL or IOH
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