PALCE26V12

www.DataSheet4U.com FINAL COM’L: H-7/10/15/20 IND: H-10/15/20 PALCE26V12 Family 28-Pin EE CMOS Versatile PAL Device DISTINCTIVE CHARACTERISTICS s 28-pin versatile PAL programmable logic device architecture s Electrically erasable CMOS technology provides half power (only 115 mA) at high speed (7.5 ns propagation delay) s 14 dedicated inputs and 12 input/output macrocells for architectural flexibility s Macrocells can be registered or combinatorial, and active high or active low s Varied product term distribution allows up to 16 product terms per output s Two clock inputs for independent functions s Global asynchronous reset and synchronous preset for initialization s Register preload for testability and built-in register reset on power-up s Space-efficient 28-pin SKINNYDIP and PLCC packages s Center VCC and GND pins to improve signal characteristics s Extensive third-party software and programmer support through FusionPLD partners GENERAL DESCRIPTION The PALCE26V12 is a 28-pin version of the popular PAL22V10 architecture. Built with low-power, highspeed, electrically-erasable CMOS technology, the PALCE26V12 offers many unique advantages. Device logic is automatically configured according to the user’s design specification. Design is simplified by design software, allowing automatic creation of a programming file based on Boolean or state equations. The software can also be used to verify the design and can provide test vectors for the programmed device. The PALCE26V12 ut...