THC63LVDF84B Receiver Datasheet

THC63LVDF84B Datasheet, PDF, Equivalent


Part Number

THC63LVDF84B

Description

(THC63LVDF64B / THC63LVDF84B) LVDS Color Host-LCD Panel Interface Receiver

Manufacture

THine Electronics

Total Page 10 Pages
Datasheet
Download THC63LVDF84B Datasheet


THC63LVDF84B
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THC63LVDF84B/THC63LVDF64B_Rev2.0
THC63LVDF84B/THC63LVDF64B
LVDS 24Bit/18Bit COLOR HOST-LCD PANEL INTERFACE RECEIVER
General Description
The THC63LVDF84B/THC63LVDF64B receiver sup-
ports wide VCC range(2.5~3.6V). At single 2.5V sup-
ply, the THC63LVDF84B/THC63LVDF64B reduces
EMI and power consumption.
The THC63LVDF84B receiver convert the four
LVDS(Low Voltage Differential Signaling) data streams
back into 28bits of CMOS/TTL data with falling edge
clock.
At a transmit clock frequency of 85MHz, 28bits of RGB
data and 4bits of LCD timing and control data
(HSYNC, VSYNC, CNTL1, CNTL2) are transmitted at
a rate of 2.3Gbps.
Also the THC63LVDF64B receiver convert the three
LVDS data streams back into 21bits of CMOS/TTL data
with falling edge clock.
At a transmit clock frequency of 85MHz, 21bits of RGB
data and 4bits of LCD timing and control data
(HSYNC, VSYNC, CNTL1, CNTL2) are transmitted at
a rate of 1.78Gbps.
Features
Wide VCC range: 2.5~3.6V
Wide dot clock range: 20-85MHz suited for VGA,
SVGA, XGA and SXGA (VCC=3.0~3.6V)
Wide dot clock range: 20-70MHz suited for VGA,
SVGA, XGA and SXGA (VCC=2.5V~3.6V)
PLL requires No external components
Rx power consumption < 80mW @VCC 2.5V,
65MHz Grayscale
Power-Down Mode
Low profile 56 Lead or 48 Lead TSSOP Package
Pin compatible with THC63LVDF84A/F64A
Block Diagram
RA +/-
DATA
(LVDS)
RB +/-
RC +/-
RD +/-
THC63LVDF84B
CMOS/TTL
OUTPUT
7 RA0-6
7 RB0-6
7 RC0-6
7 RD0-6
RA +/-
DATA
(LVDS)
RB +/-
RC +/-
THC63LVDF64B
CMOS/TTL
OUTPUT
7 RA0-6
7 RB0-6
7 RC0-6
CLOCK
(LVDS)
RCLK +/-
20 to 85MHz
PLL
RECEIVER
CLOCK OUT
(20 to 85MHz)
CLOCK
(LVDS)
RCLK +/-
20 to 85MHz
/PDWN
RECEIVER
PLL CLOCK OUT
(20 to 85MHz)
/PDWN
(140-595Mbit/On Each LVDS Channel)
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Copyright 2001-2003 THine Electronics, Inc. All rights reserved
1
THine Electronics, Inc.

THC63LVDF84B
www.DataSheet4U.com
THC63LVDF84B/THC63LVDF64B _Rev2.0
Pin Out
THC63LVDF84B
RC3
RD6
RC4
GND
RC5
RC6
RD0
LVDSGND
RA-
RA+
RB-
RB+
LVDSVCC
LVDSGND
RC-
RC+
RCLK-
RCLK+
RD-
RD+
LVDSGND
PLLGND
PLLVCC
PLLGND
/PDWN
CLKOUT
RA0
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VCC
RC2
RC1
RC0
GND
RB6
RD5
RD4
VCC
RB5
RB4
RB3
GND
RB2
RD3
RD2
VCC
RB1
RB0
RA6
GND
RA5
RD1
RA4
RA3
VCC
RA2
RA1
THC63LVDF64B
RC3
RC4
GND
RC5
RC6
N/C
LVDSGND
RA-
RA+
RB-
RB+
LVDSVCC
LVDSGND
RC-
RC+
RCLK-
RCLK+
LVDSGND
PLLGND
PLLVCC
PLLGND
/PDWN
CLKOUT
RA0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
VCC
RC2
46
45
44
43
RC1
RC0
GND
RB6
42 VCC
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
RB5
RB4
RB3
GND
RB2
VCC
RB1
RB0
RA6
GND
RA5
RA4
RA3
VCC
RA2
RA1
GND
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Copyright 2001-2003 THine Electronics, Inc. All rights reserved
2
THine Electronics, Inc.


Features www.DataSheet4U.com THC63LVDF84B/THC63L VDF64B_Rev2.0 THC63LVDF84B/THC63LVDF64 B LVDS 24Bit/18Bit COLOR HOST-LCD PANEL INTERFACE RECEIVER General Descriptio n The THC63LVDF84B/THC63LVDF64B receive r supports wide VCC range(2.5~3.6V). At single 2.5V supply, the THC63LVDF84B/T HC63LVDF64B reduces EMI and power consu mption. The THC63LVDF84B receiver conve rt the four LVDS(Low Voltage Differenti al Signaling) data streams back into 28 bits of CMOS/TTL data with falling edge clock. At a transmit clock frequency o f 85MHz, 28bits of RGB data and 4bits o f LCD timing and control data (HSYNC, V SYNC, CNTL1, CNTL2) are transmitted at a rate of 2.3Gbps. Also the THC63LVDF64 B receiver convert the three LVDS data streams back into 21bits of CMOS/TTL da ta with falling edge clock. At a transm it clock frequency of 85MHz, 21bits of RGB data and 4bits of LCD timing and co ntrol data (HSYNC, VSYNC, CNTL1, CNTL2) are transmitted at a rate of 1.78Gbps. Features • Wide VCC range: 2.5~3.6V • Wide dot clock range: 2.
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