THC63LVDF64A

www.DataSheet4U.com Version 2.10 THine THC63LVDM63A/THC63LVDF64A PRELIMINARY 85MHz LVDS 18 Bit COLOR HOST-LCD PANEL INTERFACE General Description The THC63LVDM63A transmitter converts 21 bits of CMOS/TTL data into LVDS(Low Voltage Differential Signaling) data stream. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. The THC63LVDM63A can be programmed for rising edge or falling edge clocks through a dedicated pin. The THC63LVDF64A receiver convert the LVDS data streams back into 21 bits of CMOS/TTL data with falling edge clock. At a transmit clock frequency of 85MHz, 18 bits of RGB data and 3 bits of LCD timing and control data (HSYNC, VSYNC, CNTL1) are transmitted at a rate of 595 Mbps per LVDS data channel. Features 21:3 Data channel compression at up to 223 Megabytes per sec throughput Wide Frequency Range: 20 - 85 MHz suited for VGA,SVGA,XGA and SXGA Narrow bus (8 lines) reduces cable size 345mV swing LVDS devices for Low EMI Supports Spread Spectrum Clock Generator On chip Input Jitter Filtering PLL requires No External Components Single 3.3V supply with 110mW(TYP) Low Power CMOS Design Power-Down Mode Low profile 48 Lead TSSOP Package Clock Edge Programmable for Transmitter Improved Replacement for the National DS90CF363/364 THC63LVDM63A TA0-6 TB0-6 TC0-6 7 7 7 TA+/TB+/DATA TC+/- (LVDS) THC63LVDF64A RA+/RB+/RC+/7 7 7 RA0-6 RB0-6 RC0-6 CMOS/TTL OUTPUTS CMOS/TTL INPUTS (140 To 595 Mbit/ On Each LVDS Channel) TR...