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TP6311
1/8 TO 1/16-DUTY VFD CONTROLLER
General Description
The TP6311 is a VFD (Vacuum Fluorescent Display) controller/driver that is driven on a 1/8 to 1/16-duty factor. It consists of 12 segment output lines, 8 grid output lines, 8 segment/grid output drivelines, a display memory, a control circuit, and a key scan circuit. Serial data is input to TP6311 through a This VFD controller/driver three-line serial interface. microcomputer.
Features
Multiple display modes (12-segment & 16-digit to 20-segment & 8-digit) Key scanning (12×4 matrices) Dimming circuit (eight steps) High-voltage output (VDD – 35V max) LED ports (5 chs, 20 mA max) General-purpose input port (4 bits) No external resistor necessary for driver outputs (P-ch open-drain + pull-down resistor output) Serial interface (CLK, STB, DIN, DOUT)
is ideal as a peripheral device of a single-chip
Ordering Information
TP 6311 Footprint Version Package Type Package Type Q: QFP Footprint L: 3.2 mm
Block Diagram
Command decoder DIN
Dimming circuit
16-bit output latch
DOUT Serial I/F CLK STB VDD Display memory 20 bit x 16 word
20
12
Segment driver
Seg1
Seg12
8
Segment/grid driver
Seg13/Gird16
R OSC Timing generator key scan
Data selector
8
Seg12/Gird9
16-bit output latch
Key1 to Key4
16 4
8
Grid driver
Key data memory (4 x 12)
8 Grid1
Grid8
SW1 to SW4
4 bit latch
5 bit latch VDD (+5V) LED1 LED5 VSS (0V) VEE (-30V)
4
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TP6311
1/8 TO 1/16-DUTY VFD CONTROLLER
Pin Configuration (Top View)
Grid 1 Grid 2 Grid 3 Grid 4 41 Grid 5 40 LED 1 LED 2 LED 3 LED 4 LED 5 46 VDD 45
OSC 52
51
VS VSS
50
49
48
47
44
43
SW 1 SW 2 SW 3 SW 4 DOUT DIN IC CLK STB KEY 1 KEY 2 KEY 3 KEY 4
1 2 3 4 5 6 7 8 9 10 11 12 13
42
39 38 37 36 35 34
Grid 6 Grid 7 Grid 8 Seg20/Grid9 Seg19/Grid10 VEE VDD Seg18/Grid11 Seg17/Grid12 Seg16/Grid13 Seg15/Grid14 Seg14/Grid15 Seg13/Grid16
TP6311
33 32 31 30 29 28 27
14
15
16
17
18
19
20
21
22
23
24
25 Seg11/KS11
VDD
Seg10/KS10
Use all the power pins.
Pin Description
Pin No 6 5 Symbol DIN DOUT Pin Name Date input Date output Description Input serial data at rising edge of shift clock, starting from lower bit. Outputs serial data at falling edge of shift clock, starting from lower bit. This is N-ch open-drain output pin. Initializes serial interface at rising or falling edge to make TP6311 waiting for reception of command. Data input after STB has fallen is processed as command. While command data is processed, current processing is stopped, and serial interface is initialized. While STB is high, CLK is ignored. Reads serial data at rising edge, and outputs data at falling edge. Connect resistor for determining oscillation frequency to this pin. Segment output pins (Dual function as key source) Grid output pins These pins are selectable for segment or grid output. CMOS output. +20 mA max Data input to these pins is latched at end of display cycle. These pins constitute 4-bit general-purpose input port. 5V ¡Ó 10% Connect this pin to GND of system. VDD – 35 V max Be sure to leave this pin open (this pin is at VDD level).
9
STB
Strobe
8 52 15 to 26 44 to 37
CLK OSC Seg1/KS1 to Seg12/KS12 Grid1 to Grid8
Clock input Oscillator pin High-voltage output (Segment) High-voltage output (Grid) High-voltage output (Segment/grid) LED output Key data input Switch input Logic power Logic ground Pull-down level Internally connected
27 to 32 Seg13/Grid16 to 35 to 36 Seg20/Grid9 50 to 46 LED1 to LED5 10 to 13 Key1 to Key4 1 to 4 SW1 to SW4 14, 33, 45 VDD 51 VSS 34 VEE 7 IC www.DataSheet4U.com
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Seg12/KS12
Seg1/KS1
Seg2/KS2
Seg3/KS3
Seg4/KS4
Seg5/KS5
Seg6/KS6
Seg7/KS7
Seg8/KS8
Seg9/KS9
26
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TP6311
1/8 TO 1/16-DUTY VFD CONTROLLER
Functional Description
Display RAM Address and Display Mode
The display RAM stores the data transmitted from an external device to TP6311 through the serial interface, and is assigned addresses as follows, in units of 8 bits: Seg1 Seg4 Seg8 Seg12 Seg16 Seg20 00HL 00HU 01HL 01HU 02HL DIG1 03HL 03HU 04HL 04HU 05HL DIG2 06HL 06HU 07HL 07HU 08HL DIG3 09HL 09HU 0AHL 0AHU 0BHL DIG4 0CHL 0CHU 0DHL 0DHU 0EHL DIG5 0FHL 0FHU 10HL 10HU 11HL DIG 12HL 12HU 13HL 13HU 14HL DIG7 15HL 15HU 16HL 16HU 17HL DIG8 18HL 18HU 19HL 19HU 1AHL DIG9 1BHL 1BHU 1CHL 1CHU 1DHL DIG10 1EHL 1EHU 1FHL 1FHU 20HL DIG11 21HL 21HU 22HL 22HU 23HL DIG12 24HL 24HU 25HL 25HU 26HL DIG13 27HL 27HU 28HL 28HU 29HL DIG14 2AHL 2AHU 2BHL 2BHU 2CHL DIG15 2DHL 2DHU 2EHL 2EHU 2FHL DIG16 b0 XX HL Lower 4 bits b3 b4 XX HU Higher 4 bits.
Irrelevant
KEY1 ……KEY4 KEY1 …… KEY4 Seg1 / KS1 Seg3 / KS3 Seg5 / KS5 Seg7 / KS7 Seg9 / KS9 Seg11 / KS11 b0 ……… b3 Seg2 / KS2 Seg4 / KS4 Seg6 / KS6 Seg8 / KS8 Seg10 / KS10 Seg12 / KS12 b4 ……… b7 Reading Sequence
When the most significant bit data (Seg12 b7) has been read, the least signi.