Converter Manual. DQ8020 Datasheet

DQ8020 Manual. Datasheet pdf. Equivalent

DQ8020 Datasheet
Recommendation DQ8020 Datasheet
Part DQ8020
Description MCC Manchester Code Converter Manual
Feature DQ8020; www.DataSheet4U.com 8020 8020 MCC Manchester Code Converter TM 89305 Features s Compatible with IE.
Manufacture LSI Logic
Datasheet
Download DQ8020 Datasheet





LSI Logic DQ8020
www.DataSheet4U.com
80820200
MCCTM Manchester
Code Converter
89305
Features
s Compatible with IEEE 802.3 /Ethernet (10BASE5),
IEEE802.3/Cheapernet (10BASE2) and Ethernet
Rev. 1 Specifications
s Compatible with 8003 ELDC®, 8005 Advanced
EDLC
s Manchester Data Encoding/Decoding and
Receiver Clock Recovery with Phase Locked
Loop (PLL)
s Receiver and Collision Squelch Circuit and Noise
Rejection Filter
s Differential TRANSMIT Cable Driver
s Loopback Capability for Diagnostics and
Isolation
s Fail-Safe Watchdog Timer Circuit to Prevent
Continuous Transmission
s 20 MHz Crystal Oscillator
s Transceiver Interface High Voltage (16 V)
Short Circuit Protection
Note: Check for latest Data Sheet revision
before starting any designs.
SEEQ Data Sheets are now on the Web, at
www.lsilogic.com.
This document is an LSI Logic document. Any
reference to SEEQ Technology should be
considered LSI Logic.
s Low Power CMOS Technology with Single 5V
Supply
s 20 pin DIP & PLCC Packages
Description
The SEEQ 8020 Manchester Code Converter chip pro-
vides the Manchester data encoding and decoding func-
tions of the Ethernet Local Area Network physical layer. It
interfaces to the SEEQ 8003 and 8005 Controllers and any
standard Ethernet transceiver as defined by IEEE 802.3
and Ethernet Revision 1.
Functional Block Diagram
TxEN
TxC
TxD
LPBK/
WDTD
CSN
X1
X2
RxC
RxD
COLL
WATCHDOG
TIMER
ENCODER
XTAL
CLOCK
CARRIER
SENSE
DECODER
10MHz
DETECTOR
TRANSMIT
MUX
RECEIVE
COLLISION
Figure 1. 8020 MCC Manchester Code Converter
Block Diagram.
MCC is a trademark of SEEQ Technology Inc.
wwEwD.LDCaistaarSeghiseteeret4d tUra.dceommark of SEEQ Technology Inc.
Pin Configuration
DUAL-IN LINE
TOP VIEW
Tx+
Tx–
VCC
VSS
MODE 1
Rx+
Rx–
MODE 1
GND
1
2
20 V CC
19 Tx+
LPBK/WDTD 3
18 Tx–
Rx+ 4
17 TxD
Rx–
CSN
5
6
8020
16
15
TxC
TxEN
COLL 7
14 X1
RxC 8
13 X2
RxD 9
12 COLL+
VSS 10
11 COLL–
PLASTIC LEADED CHIP CARRIER
TOP VIEW
COLL+
COLL–
3 2 1 20 19
Rx+ 4
Rx– 5
CSN 6
COLL 7
RxC 8
18 Tx–
17 TxD
16 TxC
15 TxEN
14 X1
9 10 11 12 13
MD400023/D
1



LSI Logic DQ8020
www.DataSheet4U.com
8020
The SEEQ 8020 MCC is a functionally complete Encoder/
Decoder including ECL level balanced driver and receiv-
ers, on board oscillator, analog phase locked loop for clock
recovery and collision detection circuitry. In addition, the
8020 includes a watchdog timer, a 4.5 microsecond win-
dow generator, and a loopback mode for diagnostic opera-
tion.
Together with the 8003 or 8005 and a transceiver, the 8020
Manchester Code Converter provides a high performance
minimum cost interface for any system to Ethernet.
Functional Description
The 8020 Manchester Code Converter chip has two por-
tions, transmitter and receiver. The transmitter uses
Manchester encoding to combine the clock and data into
a serial stream. It also differentially drives up to 50 meters
of twisted pair transmission line. The receiver detects the
presence of data and collisions. The 8020 MCC recovers
the Manchester encoded data stream and decodes it into
clock and data outputs. Manchester Encoding is the
process of combining the clock and data stream so that
they may be transmitted on a single twisted pair of wires,
and the clock and data may be recovered accurately upon
reception. Manchester encoding has the unique property
of a transition at the center of each bit cell, a positive going
transition for a “1”, and a negative going transition for a “0”
(See Figure 2). The encoding is accomplished by exclu-
sive-ORing the clock and data prior to transmission, and
the decoding by deriving the clock from the data with a
phase locked loop.
Clock Generator
The internal oscillator is controlled by a 20 MHz parallel
resonant crystal or by an external clock on X1. The 20 MHz
clock is then divided by 2 to generate a 10 MHz ±0.01%
transmitter clock. Both 10 MHz and 20 MHz clocks are
used in Manchester data encoding.
Manchester Encoder and Differential Output Driver
The encoder combines clock and data information for the
transceiver. In Manchester encoding, the first half of the bit
cell contains the complement of the data and the second
half contains the true data. Thus a transition is always
guaranteed in the middle of a bit cell.
Data encoding and transmission begin with TxEN going
active; the first transition is always positive for Tx(-) and
negative for Tx(+). In IEEE mode, at the termination of a
transmission, TxEN goes inactive and transmit pair ap-
proach to zero differential. In Ethernet mode, at the end of
the transmission, TxEN goes inactive and the transmit pair
stay differentially high. The transmit termination can occur
at bit cell center if the last bit is a one or at a bit boundary
if the last bit is a zero. To eliminate DC current in the
transformer during idle, Tx ± is brought to 100 mV differen-
tial in 600 ns after the last transition (IEEE mode). The
back swing voltage is guaranteed to be less than .1 V.
Watchdog Timer
A watchdog timer is built on chip. It can be enabled or
disabled by the LPBK/WDTD signal. The timer starts
counting at the beginning of the transmission. If TxEN
goes inactive before the timer expires, the timer is reset
and ready for the next transmission. If the timer expires
before the transmission ends, transmission is aborted by
disabling the differential transmitter. This is done by idling
the differential output drivers (differential output voltage
becomes zero) and deasserting CSN.
Differential Input Circuit (Rx+ and Rx–, COLL+ and
COLL–).
As shown in Figure 3, the differential input for Rx+ and Rx-
and COLL+ and COLL- are externally terminated by a pair
of 39.2 Ω ± 1% resistors in series for proper impedance
matching.
SERIAL
DATA
1
0
1 10
0
TRANSMITTED
DATA
(MANCHESTER
ENCODED)
Figure 2. Manchester Coding
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MD400023/D
2
COLLISION OR
RECEIVE
INPUT
0.01 µF
+
39.2 ± 1%
TRANSCEIVER
CABLE
39.2 ± 1%
Figure 3. Differential Input Terminator



LSI Logic DQ8020
www.DataSheet4U.com
8020
The center tap has a 0.01µF capacitor, tied to ground, to
provide the AC common mode impedance termination for
the transceiver cable.
Both collision and receiver input circuits provide a static
noise margin of -140 mV to -300mV (peak value). Noise
rejection filters are provided at both input pairs to prevent
spurious signals. For the receiver pair, the range is 15 ns
to 30 ns. For the collision pair, the range is 10 ns to 18 ns.
The D.C. threshold and noise rejection filter assure that
differential receiver data signals less than -140 mV in
amplitude or narrower than 15 ns (10 ns for collision pair)
are always rejected, signals greater than -300 mV and
wider than 30 ns (18 ns for collision pair) are always
accepted.
Manchester Decoder and Clock Recovery Circuit
The filtered data is processed by the data and clock
recovery circuit using a phase-locked loop technique. The
PLL is designed to lock onto the preamble of the incoming
signal with a transition width asymmetry not greater than
+8.25 ns to -8.25 ns within 12 bit cell times worst case and
can sample the incoming data with a transition width
asymmetry of up to +8.25 ns to -8.25 ns. The RxC high or
low time will always be greater than 40 ns. RxC follows
TxC for the first 1.2 µs and then switches to the recovered
clock. In addition, the Encoder/Decoder asserts the CSN
signal while it is receiving data from the cable to indicate
the receiver data and clock are valid and available. At the
end of the frame, after the node has finished receiving,
CSN is deasserted and will not be asserted again for a
period of 4.5 µs regardless of the state of the state of the
receiver pair or collision pair. This is called inhibit period.
There is no inhibit period after packet reception. During
clock switching, RxC may stay high for 200ns maximum.
Collision Circuit
A collision on the Ethernet cable is sensed by the trans-
ceiver. It generates a 10 MHz ±15% differential square
wave to indicate the presence of the collision. During the
collision period, CSN is asserted asynchronously with
RxC. However, if a collision arrives during inhibit period
4.5 µs from the time CSN was deasserted, CSN will not be
reasserted.
Loopback
In loopback mode, encoded data is switched to the PLL
instead of Tx+/Tx- signals. The recovered data and clock
are returned to the Ethernet Controller. All the transmit and
receive circuits, including noise rejection filter, are tested
except the differential output driver and the differential
input receiver circuits which are disabled during loopback.
At the end of frame transmission, the 8020 also generates
a 650 ns long COLL signal 550 ns after CSN was deas-
serted to simulate the IEEE 802.3 SQE test. The watchdog
timer remains enabled in this mode.
Pin Description
The MCC chip signals are grouped into four categories:
• Power Supply and Clock
• Controller Interface
• Transceiver Interface
• Miscellaneous
Power Supply
VCC ..........................................................................+5V
VSS .....................................................................Ground
X1 and X2 clock (Inputs): Clock Crystal: 20 MHz crystal
oscillator input. Alternately, pin X1 may be used at a TTL
level input for external timing by floating pint X2,
Controller Interface
RxC Receive Clock (Output): This signal is the recov-
ered clock from the phase decoder circuit. It is switched to
TxC when no incoming data is present from which a true
receive clock is derived. 10 MHz nominal and TTL compat-
ible.
RxD Receive Data (Output): The RxD signal is the
recovered data from the phase decoder. During idle
periods, the RxD pin is LOW under normal conditions. TTL
and MOS level compatible. Active HIGH.
CSN Carrier Sense (Output): The Carrier Sense Signal
indicates to the controller that there is activity on the
coaxial cable. It is asserted when receive data is present
or when a collision signal is present. It is deasserted at the
end of frame or at the end of collision, whichever occurs
later. It is asserted or deasserted synchronously with RxC.
TTL compatible.
TxC Transmit Clock (Output): A 10 MHz signal derived
from the internal oscillator. This clock is always active.
TTL and MOS level compatible.
TxD Transmit Data (Input): TxD is the NRZ serial input
data to be transmitted. The data is clocked into the MCC
by TxC. Active HIGH, TTL compatible.
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MD400023/D
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