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PMV117EN
µTrenchMOS™ enhanced logic level FET
Rev. 02 — 7 April 2005 Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS™ technology.
1.2 Features
s Logic level threshold s Subminiature surface-mounted package s Very fast switching
1.3 Applications
s Battery management s High-speed switch s Low power DC-to-DC converter
1.4 Quick reference data
s VDS ≤ 30 V s RDSon ≤ 117 mΩ (VGS = 10 V) s ID ≤ 2.5 A s Ptot ≤ 0.83 W
2. Pinning information
Table 1: Pin 1 2 3 Pinning Description gate (G) source (S) drain (D)
1 2 3
D
Simplified outline
Symbol
G
SOT23
mbb076
S
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Philips Semiconductors
PMV117EN
µTrenchMOS™ enhanced logic level FET
3. Ordering information
Table 2: Ordering information Package Name PMV117EN TO-236AB Description plastic surface mounted package; 3 leads Version SOT23 Type number
4. Limiting values
Table 3: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDS VDGR VGS ID IDM Ptot Tstg Tj IS ISM drain-source voltage (DC) drain-gate voltage (DC) gate-source voltage (DC) drain current (DC) peak drain current total power dissipation storage temperature junction temperature source (diode forward) current (DC) Tsp = 25 °C peak source (diode forward) current Tsp = 25 °C; pulsed; tp ≤ 10 µs Tsp = 25 °C; VGS = 10 V; Figure 2 and 3 Tsp = 100 °C; VGS = 10 V; Figure 2 Tsp = 25 °C; pulsed; tp ≤ 10 µs; Figure 3 Tsp = 25 °C; Figure 1 Conditions 25 °C ≤ Tj ≤ 150 °C 25 °C ≤ Tj ≤ 150 °C; RGS = 20 kΩ Min −65 −65 Max 30 30 ±20 2.5 1.6 10 0.83 +150 +150 0.8 3.3 Unit V V V A A A W °C °C A A
Source-drain diode
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9397 750 14709 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 7 April 2005
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Philips Semiconductors
PMV117EN
µTrenchMOS™ enhanced logic level FET
120 Pder (%) 80
03aa17
120 Ider (%) 80
03aa25
40
40
0 0 50 100 150 Tsp (°C) 200
0 0 50 100 150 Tsp (°C) 200
P tot P der = ------------------------ × 100 % P °
tot ( 25 C )
VGS ≥ 10 V
ID I der = -------------------- × 100 % I °
D ( 25 C )
Fig 1. Normalized total power dissipation as a function of solder point temperature
102 ID (A) 10 Limit RDSon = VDS / ID
Fig 2. Normalized continuous drain current as a function of solder point temperature
03ak56
tp = 10 µs 100 µs 1 DC 10−1 1 ms 10 ms 100 ms
10−2 10−1
1
10 VDS (V)
102
Tsp = 25 °C; IDM is single pulse
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
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9397 750 14709 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 7 April 2005
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Philips Semiconductors
PMV117EN
µTrenchMOS™ enhanced logic level FET
5. Thermal characteristics
Table 4: Rth(j-sp) Thermal characteristics Conditions Figure 4 Min Typ Max 100 Unit K/W thermal resistance from junction to solder point Symbol Parameter
103 Zth(j-sp) (K/W) 102 δ = 0.5 0.2 10 0.1 0.05 0.02 single pulse 1 10−4
P
03ak55
δ=
tp T
tp T
t
10−3
10−2
10−1
1 tp (s)
10
Fig 4. Transient thermal impedance from junction to solder point as a function of pulse duration
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9397 750 14709 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 7 April 2005
4 of 12
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Philips Semiconductors
PMV117EN
µTrenchMOS™ enhanced logic level FET
6. Characteristics
Table 5: Characteristics Tj = 25 °C unless otherwise specified. Symbol Parameter Static characteristics V(BR)DSS drain-source breakdown voltage ID = 10 µA; VGS = 0 V Tj = 25 °C Tj = −55 °C VGS(th) gate-source threshold voltage ID = 1 mA; VDS = VGS; Figure 9 and 10 Tj = 25 °C Tj = 150 °C Tj = −55 °C IDSS drain-source leakage current VDS = 24 V; VGS = 0 V Tj = 25 °C Tj = 150 °C IGSS RDSon gate-source leakage current drain-source on-state resistance VGS = ±20 V; VDS = 0 V VGS = 10 V; ID = 500 mA; Figure 6 and 8 Tj = 25 °C VGS = 4.5 V; ID = 500 mA; Figure 6 and 8 Tj = 25 °C Tj = 150 °C Dynamic characteristics Qg(tot) Qgs Qgd Ciss Coss Crss td(on) tr td(off) tf VSD trr total gate charge gate-source charge gate-drain (Miller) charge input capacitance output capacitance reverse transfer capacitance turn-on delay time rise time turn-off delay time fall time source-drain (diode forward) voltage reverse recovery time IS = 0.83 A; VGS = 0 V; Figure 12 IS = 1 A; dIS/dt = −100 A/µs; VGS = 0 V; VDS = 25 V VDD = 15 V; RL = 15 Ω; VGS = 10 V VGS = 0 V; VDS = 10 V; f = 1 MHz; Figure 13 ID = 0.5 A; VDD = 15 V; VGS = 10 V; Figure 11 4.6 0.6 1.35 147 65 41 4 7.5 18 13 0.7 69 1.2 nC nC nC pF pF pF ns ns ns ns V ns 117 188 190 300 mΩ mΩ 74 117 mΩ 0.01 10 0.5 10 100 µA µA nA 1.5 1.1 2 2.7 V V V 30 27 37 V V Conditions Min Typ Max Unit
Source-drain diod.