Audio Processor. CS4812 Datasheet

CS4812 Processor. Datasheet pdf. Equivalent

CS4812 Datasheet
Recommendation CS4812 Datasheet
Part CS4812
Description Fixed Function Multi-Effects Audio Processor
Feature CS4812; www.DataSheet4U.com CS4812 Fixed Function Multi-Effects Audio Processor Features l DSP Description.
Manufacture Cirrus Logic
Datasheet
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Cirrus Logic CS4812
www.DataSheet4U.com
CS4812
Fixed Function Multi-Effects Audio Processor
Features
l DSP for embedded reverb/effects
applications
– 24-bit Audio Processing Engine
– No External RAM required
– Two 24-bit ∆Σ ADCs with 100 dB Dyn. Range
– Two 24-bit ∆Σ DACs with 100 dB Dyn. Range
l Mono Guitar or Mixer Effects firmware
included
l Real time parameter control via messaging
protocol
l Serial Control Port for microcontroller
interface
l Single +5V supply operation
l 100-pin Metric Quad Flat Package (MQFP)
ORDERING INFO
CS4812-KM -10 to +70°C 100-pin MQFP
CDB4812 Electric Guitar Effects w/
Parameter Controls.
Description
The CS4812 is a complete audio effects processing
system on a chip. This device includes a proprietary 24-
bit audio processing engine with considerable on-chip
RAM, two ADCs and two DACs. A full-featured serial
control port allows interfacing to an external host
microcontroller. Other features such as single +5V
operation simplify system design.
The CS4812, combined with Crystal effects firmware, is
the ideal solution for a variety of effects processing
applications where user parameter control is desired.
The Crystal effects firmware provides a messaging
protocol for the serial control port that allows an external
microcontroller to have real-time parameter control over
the audio effects. The complete processor and effects
solution may be evaluated with the CDB4812
demonstration board. The CDB4812 demonstrates a
host of mono electric guitar effects including a digital
spring reverb, delay, chorus, flange and tremolo with
parameter adjustment capability. Please refer to AN195
for more information on application firmware for the
CS4812.
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ataSP.O. Box 17847, Austin, Texas 78760
.D(512) 445 7222 FAX: (512) 445 7581
www http://www.cirrus.com

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This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright Cirrus Logic, Inc. 2001
(All Rights Reserved)
JUL ‘01
DS291PP3
1



Cirrus Logic CS4812
www.DataSheet4U.com
CS4812
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 4
2. TYPICAL CONNECTION DIAGRAMS ................................................................................... 14
3. FUNCTIONAL DESCRIPTION ............................................................................................... 17
3.1 Overview .......................................................................................................................... 17
3.2 Analog Inputs ................................................................................................................... 17
3.2.1 Line Level Inputs ................................................................................................. 17
3.2.2 Digital High Pass Filter ........................................................................................ 18
3.3 Analog Outputs ................................................................................................................ 18
3.3.1 Line Level Outputs .............................................................................................. 18
3.4 Clock Generation ............................................................................................................. 19
3.4.1 Clock Source ....................................................................................................... 19
3.5 Serial Control Port ............................................................................................................ 19
3.5.1 SPI Bus ............................................................................................................... 19
3.5.1.1 SPI Master Mode ................................................................................ 20
3.5.1.2 SPI Slave Mode .................................................................................. 20
3.5.2 I2C Bus ................................................................................................................ 23
3.5.2.1 I2C Master Mode ................................................................................. 23
3.5.2.2 I2C Slave Mode ................................................................................... 24
3.6 Boot Modes ...................................................................................................................... 26
3.6.1 AutoBoot ............................................................................................................. 26
3.6.2 HostBoot ............................................................................................................. 26
3.7 Resets ............................................................................................................................. 27
4. POWER SUPPLY AND GROUNDING ................................................................................... 28
5. PIN DESCRIPTIONS .............................................................................................................. 29
6. PARAMETER DEFINITIONS .................................................................................................. 33
7. PACKAGE DIMENSIONS ...................................................................................................... 34
LIST OF FIGURES
Figure 1. SPI Control Port Slave Mode Timing .......................................................... 8
Figure 2. SPI Control Port Master Mode (AutoBoot) Timing ..................................... 9
Figure 3. I2C® Control Port Slave Mode Timing ...................................................... 11
Figure 4. I2C® Control Port Master Mode (AutoBoot) Timing .................................. 12
Figure 5. Typical Connection Diagram, Control Port Slave Mode ........................... 14
Figure 6. Typical Connection Diagram, Control Port I2C Master Mode ................... 15
Figure 7. Typical Connection Diagram, Control Port SPI Master Mode .................. 15
Figure 8. Typical Connection Diagram, Control Port I2C Slave Mode ..................... 16
Figure 9. Typical Connection Diagram, Control Port SPI Slave Mode .................... 16
Figure 10.Recommended Line Input Buffer .............................................................. 17
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
mhttp://www.cirrus.com/corporate/contacts/
.coPreliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product infor-
mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information
Ucontained in this document is accurate and reliable. However, the information is subject to change without notice and is provided AS ISwithout warranty of any
t4kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third
parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publi-
ecation may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise)
without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the
eprintout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photo-
hgraphic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or
Ssale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in
this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade-
tamarks and service marks can be found at http://www.cirrus.com.
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Cirrus Logic CS4812
www.DataSheet4U.com
CS4812
Figure 11.Single Ended Input ................................................................................... 18
Figure 12.Butterworth Output Filters ........................................................................ 18
Figure 13.Output Mute Circuit .................................................................................. 19
Figure 14.Control Port Timing, SPI Master Mode AutoBoot ..................................... 20
Figure 15.Control Port Timing, SPI Slave Mode Write ............................................. 20
Figure 16.SPI Slave Write Flow Diagram ................................................................. 21
Figure 17.Control Port Timing, SPI Slave Mode Read ............................................. 21
Figure 18.SPI Slave Mode Read Flow Diagram........................................................ 22
Figure 19.SPI Slave Mode Read Flow Diagram with DSP REQ .............................. 22
Figure 20.Control Port Timing, I2C Master Mode AutoBoot ..................................... 23
Figure 21.I2C Slave Mode Write Flow Diagram ........................................................ 24
Figure 22.Control Port Timing, I2C Slave Mode Write .............................................. 24
Figure 23.Control Port Timing, I2C Slave Mode Write .............................................. 24
Figure 24.I2C Slave Mode Read Flow Diagram ....................................................... 25
Figure 25.I2C Slave Mode Read Flow Diagram with DSP REQ ............................... 26
Figure 26.HostBoot Flow Diagram ........................................................................... 27
Figure 27.CS4812 Suggested Layout ...................................................................... 28
Figure 28.Pin Assignments ...................................................................................... 29
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