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FAN5078 DDR/ACPI Regulator Combo
May 2006
FAN5078 DDR/ACPI Regulator Combo
Features
PWM regulator for VDDQ (2.5V or 1.8) Linear LDO regulator generates VTT = VDDQ/2, 1.5A Peak sink/source capability AMT / M-state support Control to generate 5V USB ACPI drive and control for 5V DUAL generation 3.3V internal LDO for 3V-ALW generation 300 kHz fixed frequency switching RDS(ON) current sensing or optional current sense resistor for precision over-current detect Internal synchronous boot diode Common Power Good signal for all voltages Input under-voltage lockout (UVLO) Thermal shutdown Latched multi-fault protection Precision reference output for ULDO controllers 24-pin 5 x 5 MLP package
Description
The FAN5078 DDR memory regulator combines a highefficiency Pulse-Width Modulated (PWM) controller to generate the memory supply voltage, VDDQ, and a linear regulator to generate termination voltage (VTT). Synchronous rectification provides high efficiency over a wide range of load currents. Efficiency is further enhanced by using the low-side MOSFET’s RDS(ON) to sense current. The VDDQ PWM regulator is a sampled current mode control with external compensation to achieve fast load-transient response and provide system design optimization. The VTT regulator derives its reference and takes its power from the VDDQ PWM regulator, output. The VTT termination regulator is capable of sourcing or sinking 1.5A peak currents. In S5 M1 mode, the VDDQ switcher, VTT regulator, and the 3.3V regulators remain on. S3 mode keeps these regulators on, but also turns on an external P-Channel to provide 5V USB. A single soft-start capacitor enables controlled slew rates for both VDDQ and 3.3V-ALW outputs. PGOOD becomes true in S0 only after all regulators have achieved stable outputs. In S5 (EN = 0), the 3.3V internal LDO stays on while the other regulators are powered down.
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Ordering Information
Part Number
FAN5078MPX
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Applications DDR VDDQ and
VTT voltage generation with ACPI
Temperature Range
-10°C to 85°C
Package
MLP-24 5x5mm
Packing
Tape and Reel
w.D a
© 2006 Fairchild Semiconductor Corporation FAN5078 Rev. 1.0.0 • 05/09/06
www.fairchildsemi.com
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FAN5078 DDR/ACPI Regulator Combo
Block Diagrams
R4
+5VSB +12V
+5MAIN S3#O
Q4 C13
Q7
+5VSB SBSW
Q6
+5MAIN S3#O 3 1 16 18 17 15 13 9 10 C3 SS VCC 21 14 11 HDRV SW ISNS R3 Q2 LDRV GND FB C9 COMP VDDQ IN REF IN VTT SNS VTT OUT C7 C8
R10 Q3
5V USB
C14 C15
SBUSB# 3.3 MAIN
Q5
4
5V MAIN S4ST# BOOT Q1 C5 C2 5V DUAL
L2
S3#O EN S3#I 3.3 ALW PGOOD
ACPI CONTROL & LOGIC
2 8
CIN
C12
L1
VDDQ COUT
+5VSB
PWM
C4 R5 ILIM
12 P1 23 22 7
R2 R1 R6 C6
R9
20
VTT LDO
24 5 6
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Figure 1. Typical DDR/ACPI System Regulation Schematic Components are selected for a 15A VDDQ output.
© 2006 Fairchild Semiconductor Corporation FAN5078 Rev. 1.0.0 • 05/11/06
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