UP/DOWN COUNTER. 54LS193 Datasheet

54LS193 COUNTER. Datasheet pdf. Equivalent

Part 54LS193
Description PRESETTABLE 4-BIT BINARY UP/DOWN COUNTER
Feature PRESETTABLE BCD/DECADE UP/DOWN COUNTER PRESETTABLE 4-BIT BINARY UP/DOWN COUNTER The SN54/74LS192 is .
Manufacture ETC
Datasheet
Download 54LS193 Datasheet



54LS193
PRESETTABLE BCD/DECADE
UP/DOWN COUNTER
PRESETTABLE 4-BIT BINARY
UP/DOWN COUNTER
The SN54/74LS192 is an UP/DOWN BCD Decade (8421) Counter and the
SN54/74LS193 is an UP/DOWN MODULO-16 Binary Counter. Separate
Count Up and Count Down Clocks are used and in either counting mode the
www.DataSheet4cUir.ccuoimts operate synchronously. The outputs change state synchronous with
the LOW-to-HIGH transitions on the clock inputs.
Separate Terminal Count Up and Terminal Count Down outputs are
provided which are used as the clocks for a subsequent stages without extra
logic, thus simplifying multistage counter designs. Individual preset inputs
allow the circuits to be used as programmable counters. Both the Parallel
Load (PL) and the Master Reset (MR) inputs asynchronously override the
clocks.
Low Power . . . 95 mW Typical Dissipation
High Speed . . . 40 MHz Typical Count Frequency
Synchronous Counting
Asynchronous Master Reset and Parallel Load
Individual Preset Inputs
Cascading Circuitry Internally Provided
Input Clamp Diodes Limit High Speed Termination Effects
CONNECTION DIAGRAM DIP (TOP VIEW)
V CC
16
P0
15
MR TC D TC U PL
14 13 12 11
P2 P3
10 9
1 2 3 4 56
78
P 1 Q 1 Q 0 CP D CP U Q 2 Q 3 GND
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
PIN NAMES
LOADING (Note a)
HIGH
LOW
CPU
CPD
MR
Count Up Clock Pulse Input
Count Down Clock Pulse Input
Asynchronous Master Reset (Clear) Input
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
PL Asynchronous Parallel Load (Active LOW) Input 0.5 U.L. 0.25 U.L.
Pn
Qn
TCD
TCU
Parallel Data Inputs
Flip-Flop Outputs (Note b)
Terminal Count Down (Borrow) Output (Note b)
Terminal Count Up (Carry) Output (Note b)
0.5 U.L.
10 U.L.
10 U.L.
10 U.L.
0.25 U.L.
5 (2.5) U.L.
5 (2.5) U.L.
5 (2.5) U.L.
NOTES:
a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
b. Temperature Ranges.
SN54/74LS192
SN54/74LS193
PRESETTABLE BCD/ DECADE
UP/ DOWN COUNTER
PRESETTABLE 4-BIT BINARY
UP/ DOWN COUNTER
LOW POWER SCHOTTKY
16
1
J SUFFIX
CERAMIC
CASE 620-09
16
1
N SUFFIX
PLASTIC
CASE 648-08
16
1
D SUFFIX
SOIC
CASE 751B-03
ORDERING INFORMATION
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
Ceramic
Plastic
SOIC
LOGIC SYMBOL
11 15 1 10 9
PL P 0 P 1 P 2 P 3
5 CP U
TC U
12
4 CP D
TC D
13
MR Q 0 Q 1 Q 2 Q 3
14 3 2 6 7
V CC = PIN 16
GND = PIN 8
FAST AND LS TTL DATA
5-351



54LS193
SN54/74LS192 SN54/74LS193
STATE DIAGRAMS
0123
15
14
13
www.DataSheet4U.com
12 11
10
9
LS192
4
5
6
7
8
LS192 LOGIC EQUATIONS
FOR TERMINAL COUNT
TCU = Q0 Q3 CPU
TCD = Q0 Q1 Q2 Q3 CPD
LS193 LOGIC EQUATIONS
FOR TERMINAL COUNT
TCU = Q0 Q1Q2Q3 CPU
TCD = Q0 Q1 Q2 Q3 CPD
COUNT UP
COUNT DOWN
0123
15
14
13
12 11 10
9
LS193
4
5
6
7
8
LOGIC DIAGRAMS
P L 11
(LOAD)
CP U
(UP COUNT)
5
P0
15
P1
1
P2
10
P3
9
12 TC U
(CARRY
OUTPUT)
S
D
Q
T
Q
C
D
S
D
Q
T
Q
C
D
S
D
Q
T
Q
C
D
S
D
Q
T
Q
C
D
CP D
(DOWN
4
COUNT)
MR
14
(CLEAR)
V CC = PIN 16
GND = PIN 8
= PIN NUMBERS
3
Q0
2
Q1
LS192
6
Q2
13 TC D
(BORROW
OUTPUT)
7
Q3
FAST AND LS TTL DATA
5-352





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