Document
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Preliminary
Notice: This is not a final specification. Some parametric limits are subject to change.
Renesas LSIs
M6MGB/T33BS8AWG-P
33,554,432-BIT (2,097,152-WORD BY 16-BIT) CMOS FLASH MEMORY 8,388,608-BIT (524,288-WORD BY 16-BIT) CMOS SRAM Stacked-CSP (Chip Scale Package) &
Description
The M6MGB/T33BS8AWG-P is a Stacked Chip Scale Package (S-CSP) that contents 32M-bit Flash memory and 8M-bit SRAM in a 66-pin Stacked CSP with leaded solder ball. 32M-bit Flash memory is a 2,097,152 words, single power supply and high performance non-volatile memory fabricated by CMOS technology for the peripheral circuit and DINOR (Divided bit-line NOR) architecture for the memory cell. All memory blocks are locked and can not be programmed or erased, when F-WP# is Low. Using Software Lock Release function, program or erase operation can be executed. 8M-bit SRAM is a 524,288 words asynchronous SRAM fabricated by CMOS technology. The M6MGB/T33BS8AWG-P is suitable for a high performance cellular phone and a mobile PC that are required to be small mounting area, weight and small power dissipation.
Features
Access Time Flash SRAM 70ns (Max.) 85ns (Max.) F-VCC =VCC=2.7 ~ 3.0V Ta=-40 ~ 85 °C 66 pin S-CSP Ball pitch 0.80mm Outer-ball:Sn - Pb
Supply Voltage Ambient Temperature Package
Application
Mobile communication products
PIN CONFIGURATION (TOP VIEW)
INDEX(Laser Marking)
A B C D E
NC NC NC A5 A4 A0
F-CE#
NC NC A18 S-LB#
F-WP# S-GND F-WE#
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A17 S-UB# A7 A6 A3 A2 A1 DQ9 DQ8 DQ0
DQ10
A16 A8
F-A20
NC
F-RP#
F-RY/BY#
A11
S-OE#
F-A19
A10 A9
DQ12 DQ13 DQ15
A15 A14 A13 A12
F-GND
11.0 mm
F G H J K L M
DQ11
F-GND
S-CE2
DQ6 DQ4 DQ5
S-WE#
F-OE#
DQ2 DQ3
S-VCC
DQ14
NC NC NC
S-CE1# DQ1
F-VCC
DQ7
NC NC NC
NC:Non Connection
1 2 3 4 5 6 7 8
8.0 mm F-VCC S-VCC F-GND S-GND A0-A18 F-A19-F-A20 DQ0-DQ15 F-CE# S-CE1# S-CE2 : VCC for Flash Memory : VCC for SRAM : GND for Flash Memory : GND for SRAM : Common address for Flash/SRAM : Address for Flash : Data I/O : Flash chip enable : SRAM chip enable1 : SRAM chip enable2 F-OE# S-OE# F-WE# S-WE# F-WP# F-RP# F-RY/BY# S-LB# S-UB# :Output enable for Flash :Output enable for SRAM :Write enable for Flash :Write enable for SRAM :Write protect for Flash :Reset power down for Flash :Flash Ready/Busy :Lower byte control for SRAM :Upper byte control for SRAM
1
Rev.0.2_48a_bebz
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Preliminary
Notice: This is not a final specification. Some parametric limits are subject to change.
Renesas LSIs
M6MGB/T33BS8AWG-P
33,554,432-BIT (2,097,152-WORD BY 16-BIT) CMOS FLASH MEMORY 8,388,608-BIT (524,288-WORD BY 16-BIT) CMOS SRAM Stacked-CSP (Chip Scale Package) &
MCP Block Diagram
F-Vcc
F-GND
A0 to A20 A0 to A20 F-CE# F-WP# F-RP# F-WE# F-OE#
32Mbit DINOR Flash Memory
F-RY/BY#
DQ0 to DQ15 S-Vcc S-GND
S-WE# S-OE# S-UB# S-LB# S-CE1# S-CE2
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A0 to A18 8Mbit SRAM
Note: In the data sheet there are “VCC”s w.