CMOS SRAM
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Preliminary
Notice: This is not a final specification. Some parametric limits are subject to change...
Description
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Preliminary
Notice: This is not a final specification. Some parametric limits are subject to change.
Renesas LSIs
M6MGB/T33BS8BWG
33,554,432-BIT (2,097,152-WORD BY 16-BIT) CMOS FLASH MEMORY 8,388,608-BIT (524,288-WORD BY 16-BIT) CMOS SRAM Stacked-CSP (Chip Scale Package) &
Description
The M6MGB/T33BS8BWG is a Stacked Chip Scale Package The M6MGB/T33BS8BWG is suitable for a high performance cellular phone and a mobile PC that are required to be small (S-CSP) that contents 32M-bit Flash memory and 8M-bit mounting area, weight and small power dissipation. SRAM in a 66-pin Stacked CSP for lead free use. 32M-bit Flash memory is a 2,097,152 words, single power supply and high performance non-volatile memory fabricated by CMOS technology for the peripheral circuit and DINOR (Divided bit-line NOR) architecture for the memory cell. All memory blocks are locked and can not be programmed or erased, when F-WP# is Low. Using Software Lock Release function, program or erase operation can be executed. 8M-bit SRAM is a 524,288 words asynchronous SRAM fabricated by CMOS technology.
Features
Access Time Flash SRAM 70ns (Max.) 85ns (Max.) F-VCC =VCC=2.7 ~ 3.0V Ta=-40 ~ 85 °C 66 pin S-CSP Ball pitch 0.80mm Outer-ball:Sn – Ag-Cu
Supply Voltage Ambient Temperature Package
Application
Mobile communication products
PIN CONFIGURATION (TOP VIEW)
INDEX(Laser Marking)
A B C D E
NC NC NC A5 A4 A0
F-CE#
NC NC A18 A17 A7 A6 A3 A2 A1
S-CE1# S-LB# F-WP# S-GND F-WE#
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