OTP EPROM. AN620 Datasheet
ON-BOARD PROGRAMMING OF OTP EPROM
by Franco MORANDI
In recent years interest has been growing in On-Board Programming of OTP EPROM memories. There
are two main factors which have stimulated this interest: the growth of the FLASH Memory market and the
increased use of surface mount packages.
THE GROWTH OF THE FLASH MEMORY MARKET
UV EPROMs and OTP EPROMs offer a higher degree of flexibility compared to Mask ROMs. This is due
to their ability to be electrically programed and, in the case of the UV EPROM, erased by exposure to UV
light, then re-programed. The ability to electrically program these parts is the most important feature which
allows UV EPROMs or OTP EPROMs to be seen by users as ROMs which are programmable at the final
moment in the exact quantity required.
Programming of the memories is mainly done by the use of dedicated programing equipment using software
algorithms which match those specified by the major chip makers. Fast programming services are also
offered by testing houses and by vendors themselves for a small price premium.
The plastic packaged OTP EPROMs are therefore regarded by many as ’flexible ROMs’.
Programming of OTP EPROMs in the application board itself, rather than in the dedicated programming
equipment, has not been common until the recent introduction of FLASH Memories. One of the important
www.DataSheet4U.comfeatures of the FLASH Memory is its programability (and erase and re-programability) on board, in the
application. With the growth in the use of FLASH Memories today, OTP EPROMs are seen not only as
flexible ROMs but now also as low cost FLASH Memory alternatives. For this reason many customers plan
to use OTP EPROMs to replace FLASH Memories in low end applications as soon as production levels
increase and codes become stable. These OTP EPROMs are mounted on board and thus must be
programmed, like the FLASH Memory, in the application.
THE INCREASED USE OF SURFACE MOUNT PACKAGES
While the traditional Dual-In-Line insertion packages, both ceramic and plastic, remain popular, there is a
strong trend towards surface mounting PLCC and TSOP types which offer small footprints and easy
automatic assembly. The loading of these packages in the dedicated programming equipment and
subsequent transfer to the application board, however, presents significant problems and expensive,
dedicated handlers are needed. Users therefore prefer to abandon ’off line’ programming and chose
On-Board Programming techniques.
Programming a UV EPROM or OTP EPROM cell is performed by injecting electrons onto the cell MOS
transistor floating gate. A voltage in excess of 6V must be applied to the drain of the cell, together with
above 12V on the control gate to get an average energy of the electrons sufficiently large to make them
jump the oxide barrier at a significant rate for a fast programming speed.
AN620 - APPLICATION NOTE
OBP AND PRODUCT TESTING
When UV EPROM or OTP EPROM products are programmed in dedicated programming equipment the
VCC supply voltage is raised to 6V to 6.5V. This level of VCC cannot generally be applied to a board containing
the OTP EPROM due to the possible damage to other components. Recent designs of UV EPROM and
OTP EPROMs however derive the internal 6V or more used during the write mode from the VPP supply
and so are independent of the VCC voltage applied. In fact cell writing can normally take place even if the
VCC is 5V or lower.
This feature is not, however, sufficient to guarantee On-Board Programming (OBP) performance. There
remains the need to verify the memory content of programmed cells. When the read verify is performed
with a 5V VCC supply clearly this ensures that the cells are programmed to logic ’0’ at least up to 5V, but
not more. A high level of confidence remains that the cells, programmed with the internal 6 Volts derived
from the 12.75V VPP supply, are in fact over-programmed with a satisfactory margin and would display the
correct pattern if verified at above 5V VCC, but to guarantee this to a high quality level is not possible with
a read verify at 5V. Just one cell in 4 billion which is harder to program and is marginally written is sufficient
to give reject quality of 1000 ppm for 4 Megabit OTP EPROMs!
So the challenge to provide OBP features for OTP EPROMs is not one of programming, but of testing and
verification of the programmed pattern. The question that must be answered is "is it possible to guarantee
the quality of the memory content when they are programmed at 5V VCC on board?".
RELIABLE OTP EPROMS
The use of OBP for programming UV EPROMs or OTP EPROMs is to related to the confidence in the
supplier to deliver a reliable and consistent product. The following section outlines the main issues which
have been developed and are used by SGS-THOMSON to build confidence in the product’s ability to
www.DataSheet4U.comperform reliably after On-Board Programming has been used.
WAFER LEVEL TESTING
While built-in reliability is obtained for our UV EPROM and OTP EPROM products through robust design,
proven and stable processes and extensive characterisation, there are some specific routines that are used
to ensure the quality of the product for On-Board Programming.
GATE STRESS AND DRAIN STRESS
The integrity of the critical thin oxides is checked by specially developed stress tests, these are performed
by applying a fixed voltage to either the control gate (Gate Stress) or to the drains of the cells (Drain Stress).
The gate stress is done firstly on the virgin cells (All "1"s) and then on programmed cells (All "0"s). Figures
1, 2, 3 describe the different stresses, the measurements and the specific defects they aim to detect or
These tests are particularly effective in screening out the chips which are potentially prone to programming
errors because the same kind of stresses are applied to the cells during normal write operations. All the
cells of the same row share a common word line and when a byte is programmed all those cells not being
written, in the row which is at high VPP, are submitted to a gate stress and could evidence the spurious
effect of charge gain for virgin cells or charge loss for written cells. A similar argument applies for the cells
of a column, biased at the same VCC through the common bit line.
The stress times have been chosen to be equivalent to the total duration of the critical conditions
encountered whenever writing of a whole memory pattern occurs.