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ST90158 - ST90135
8/16-BIT MCU FAMILY WITH UP TO 64K ROM/OTP/EPROM AND UP TO 2K RAM
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Register File based 8/16 bit Core Architecture with RUN, WFI, SLOW and HALT modes 0 - 16 MHz Operation @ 5V±10%, -40°C to +85°C and 0°C to +70°C Operating Temperature Ranges 0 - 14 MHz Operation @ 3V±10% and 0°C to +70°C Operating Temperature Range Fully Programmable PLL Clock Generator, with Frequency Multiplication and low frequency, low cost external crystal Minimum 8-bit Instruction Cycle time: 83ns - (@ 24 MHz internal clock frequency) Minimum 16-bit Instruction Cycle time: 250ns (@ 24 MHz internal clock frequency) Internal Memory: – EPROM/OTP/ROM 16/24/32/48/64K bytes – ROMless version available – RAM 512/768/1K/1.5K/2K bytes Maximum External Memory: 64K bytes 224 general purpose registers available as RAM, accumulators or index pointers (register file) 80-pin Plastic Quad Flat Package and 80-pin Thin Quad Flat Package 67 fully programmable I/O bits 8 external and 1 Non-Maskable Interrupts DMA Controller and Programmable Interrupt Handler Single Master Serial Peripheral Interface Two 16-bit Timers with 8-bit Prescaler, one usable as a Watchdog Timer (software and hardware) Three (ST90158) or two (ST90135) 16-bit Multifunction Timers, each with an 8 bit prescaler, 12 operating modes and DMA capabilities 8 channel 8-bit Analog to Digital Converter, with Automatic voltage monitoring capabilities and external reference inputs Two (ST90158) or one (ST90135) Serial Communication Interfaces with asynchronous, synchronous and DMA capabilities Rich Instruction Set with 14 Addressing modes Division-by-Zero trap generation
TQFP80
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Versatile Development Tools, including Assembler, Linker, C-compiler, Archiver, Source Level Debugger and Hardware Emulators with Real-Time Operating System available from Third Parties DEVICE SUMMARY
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DEVICE
Program RAM Memory MFT SCI PACKAGE (Bytes) (Bytes) 16K ROM 512 768 1K 1.5K 2K 2K 2K 2K 2K 2K 2 2 2 3 3 3 3 3 3 3 1 1 1 2 2 2 2 2 2 2 PQFP80/ TQFP80 CQFP80 CQFP80 PQFP80 PQFP80/ TQFP80/ PQFP80/ TQFP80 PQFP80 24K ROM 32K ROM 48K ROM
ST90135
ST90158 ST90E158
64k ROM
64K EPROM 64K ST90E158LV EPROM ST90T158 64K OTP ST90T158LV 64K OTP ST90R158 ROMless
Rev. 3.0
January 2000 1/190
9
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Table of Contents
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1.1 ST9+ Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1.2 Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1.3 system Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1.4 I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1.5 Multifunction Timers (MFT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1.6 Standard Timer (STIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1.7 Watchdog Timer (WDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1.8 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1.9 Serial Communications Controllers (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1.10 Analog/Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.3 I/O PORT PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 DEVICE ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.1 CORE ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2 MEMORY SPACES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2.1 Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2.2 Register Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.3 SYSTEM REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.1 Central Interr.