MCM514256A

MOTOROLA SEMICONDUCTOR TECHNICAL DATA 256K x 4 Bit CMOS Dynamic RAM Page Mode, Commercial and Industrial Temperature Range The MCM514256A is a 1.0µ CMOS high-speed dynamic random access memory. It is organized as 262,144 four-bit words and fabricated with CMOS silicon-gate process technology. Advanced circuit design and fine line processing provide high performance, improved reliability, and low cost. The MCM514256A requires only nine address lines; row and column address inputs are multiplexed. The device is packaged in a 300 mil SOJ plastic package. Three-State Data Output Fast Page Mode TTL-Compatible Inputs and Output RAS-Only Refresh CAS Before RAS Refresh Hidden Refresh 512 Cycle Refresh: MCM514256A = 8 ms MCM51L4256A = 64 ms Unlatched Data Out at Cycle End Allows Two Dimensional Chip Selection Fast Access Time (tRAC): MCM514256A-70 and MCM51L4256A-70 = 70 ns (Max) MCM514256A-80 and MCM51L4256A-80 = 80 ns (Max) Low Active Power Dissipation: MCM514256A-70 and MCM51L4256A-70 = 440 mW (Max) MCM514256A-80 and MCM51L4256A-80 = 385 mW (Max) Low Standby Power Dissipation: MCM514256A and MCM51L4256A = 11 mW (Max), TTL Levels MCM514256A = 5.5 mW (Max), CMOS Levels MCM51L4256A = 1.1 mW (Max), CMOS Levels Order this document by MCM514256A/D MCM514256A MCM51L4256A N PACKAGE 300 MIL SOJ CASE 822-03 PIN NAMES A0 – A8 . . . . . . . . . . . . . . . . . . Address Input DQ0 – DQ3 . . . . . . . . . . . Data Input/Output G . . . . . . . . . . . . . . . . . . . . . ...