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AT49LV1024A Dataheets PDF



Part Number AT49LV1024A
Manufacturers ATMEL Corporation
Logo ATMEL Corporation
Description (AT49LV1024A / AT49BV1024A) 1-megabit (64K x 16) 3-volt Only Flash Memory
Datasheet AT49LV1024A DatasheetAT49LV1024A Datasheet (PDF)

www.DataSheet4U.com Features • • • • • • • • • • Single-voltage Operation Read/Write Operation: 2.7V to 3.6V (BV). 3.0V to 3.6V(LV) Fast Read Access Time – 45 ns Internal Program Control and Timer 8K Word Boot Block with Lockout Fast Erase Cycle Time – 1.5 Seconds Word-by-word Programming – 20 µs/Word Typical Hardware Data Protection Data Polling for End of Program Detection Small 10 x 14 mm VSOP Package Typical 10,000 Write Cycles Description The AT49BV/LV1024A is a 3-volt only in-system Flas.

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www.DataSheet4U.com Features • • • • • • • • • • Single-voltage Operation Read/Write Operation: 2.7V to 3.6V (BV). 3.0V to 3.6V(LV) Fast Read Access Time – 45 ns Internal Program Control and Timer 8K Word Boot Block with Lockout Fast Erase Cycle Time – 1.5 Seconds Word-by-word Programming – 20 µs/Word Typical Hardware Data Protection Data Polling for End of Program Detection Small 10 x 14 mm VSOP Package Typical 10,000 Write Cycles Description The AT49BV/LV1024A is a 3-volt only in-system Flash memory. The 1-megabit of memory is organized as 65,536 words by 16 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the devices offer access times to 45 ns with power dissipation of just 72 mW over the industrial temperature range. To allow for simple in-system reprogrammability, the AT49BV/LV1024A does not require high input voltages for programming. Three-volt-only commands determine the read and programming operation of the device. Reading data out of the device is similar to reading from an EPROM. Reprogramming the AT49BV/LV1024A is performed by erasing a block of data (entire chip or main memory block) and then programming on a word by word basis. The typical word programming time is a fast 20 µs. The end of a program cycle can be optionally detected by the Data Polling feature. Once the end of a word program cycle has been detected, a new access for a read or program can begin. The typical number of program and erase cycles is in excess of 10,000 cycles. The optional 8K word boot block section includes a reprogramming write lock out feature to provide data integrity. The boot sector is designed to contain user secure code, and when the feature is enabled, the boot sector is permanently protected from being erased or reprogrammed. 1-megabit (64K x 16) 3-volt Only Flash Memory AT49BV1024A AT49LV1024A www.DataSHeet4U.com Rev. 3332B–FLASH–12/03 Pin Configurations Pin Name A0 - A15 CE OE WE Function Addresses Chip Enable Output Enable Write Enable Data Inputs/Outputs No Connect AT49BV/LV1024A VSOP Top View Type 1 10 x 14 mm A9 A10 A11 A12 A13 A14 A15 NC WE VCC NC CE I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 I/O8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 GND A8 A7 A6 A5 A4 A3 A2 A1 A0 OE I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 GND ww.DataSheet4U.com I/O0 - I/O15 NC 1 www.DataSheet4U.com www.DataSheet4U www.DataSheet4U.com 4U.com DataSheet 4 U .com www.DataSheet4U.com Block Diagram VCC GND OE WE CE DATA INPUTS/OUTPUTS I/O15 - I/O0 16 OE, CE, AND WE LOGIC DATA LATCH INPUT/OUTPUT BUFFERS Y-GATING FFFFH MAIN MEMORY (56K WORDS) OPTIONAL BOOT BLOCK (8K WORDS) 2000H 1FFFH 0000H Y DECODER ADDRESS INPUTS X DECODER Device Operation CHIP ERASE: When the boot block programming lockout feature is not enabled, the boot block and the main memory block will erase together from the same Chip Erase command (See Command Definitions table). If the boot block lockout function has been enabled, data in the boot section will not be erased. However, data in the main memory section will be erased. After a chip erase, the device will return to the read mode. MAIN MEMORY ERASE: As an alternative to the chip erase, a main memory block erase can be performed, which will erase all words not located in the boot block region to an FFFFH. Data located in the boot region will not be changed during a main memory block erase. The Main Memory Erase command is a six-bus cycle operation. The address (555H) is latched on the falling edge of the sixth cycle while the 30H data input is latched on the rising edge of WE. The main memory erase starts after the rising edge of WE of the sixth cycle. Please see Main Memory Erase cycle waveforms. The main memory erase operation is internally controlled; it will automatically time to completion. WORD PROGRAMMING: Once the memory array is erased, the device is programmed (to a logic “0”) on a word-by-word basis. Please note that a data “0” cannot be programmed back to a “1”; only erase operations can convert “0”s to “1”s. Programming is accomplished via the internal device command register and is a four-bus cycle operation (please refer to the Command Definitions table). The device will automatically generate the required internal program pulses. The program cycle has addresses latched on the falling edge of WE or CE, whichever occurs last, and the data latched on the rising edge of WE or CE, whichever occurs first. Programming is completed after the specified tBP cycle time. The Data Polling feature may also be used to indicate the end of a program cycle. BOOT BLOCK PROGRAMMING LOCKOUT: The device has one designated block that has a programming lockout feature. This feature prevents programming of data in the designated block once the feature has been enabled. The size of the block is 8K words. This block, referred to as the boot block, can contain secure code that is used to bring up the system. Enabling the lock.


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