EP1810LC Datasheet (data sheet) PDF





EP1810LC Datasheet, EPLD Family

EP1810LC   EP1810LC  

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www.DataSheet4U.com Classic ® EPLD Fa mily Data Sheet May 1999, ver. 5 Feat ures s s s s s s s s s s Complete device family with logic densities of 3 00 to 900 usable gates (see Table 1) De vice erasure and reprogramming with non -volatile EPROM configuration elements Fast pin-to-pin logic delays as low as 10 ns and counter frequencies as high a s 100 MHz 24 to 68 pins avail

EP1810LC Datasheet, EPLD Family

EP1810LC   EP1810LC  
able in dual in-line package (DIP), plas tic J-lead chip carrier (PLCC), pin-gri d array (PGA), and small-outline integr ated circuit (SOIC) packages Programmab le security bit for protection of propr ietary designs 100% generically tested to provide 100% programming yield Progr ammable registers providing D, T, JK, a nd SR flipflops with individual clear a nd clock controls Software d








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