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Sigma-Delta ADC. AD7760 Datasheet

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Sigma-Delta ADC. AD7760 Datasheet






AD7760 ADC. Datasheet pdf. Equivalent




AD7760 ADC. Datasheet pdf. Equivalent





Part

AD7760

Description

100 dB Sigma-Delta ADC



Feature


www.DataSheet4U.com 2.5 MSPS, 20-Bit Σ ∆ ADC Preliminary Technical Data FEAT URES High performance 20-bit Sigma-Delt a ADC 118dB SNR at 78kHz output data ra te 100dB SNR at 2.5MHz output data rate 2.5 MHz maximum fully filtered output word rate Programmable over-sampling ra te (8x to 256x) Flexible parallel inter face Fully differential modulator input On-chip differential.
Manufacture

Analog Devices

Datasheet
Download AD7760 Datasheet


Analog Devices AD7760

AD7760; amplifier for signal buffering Low pass FIR filter with default or user progra mmable coefficients Over-range alert bi t Digital offset and gain correction re gisters Filter bypass modes Low power a nd power down modes Synchronization of multiple devices via SYNC pin VIN- VIN+ AD7760 FUNCTIONAL BLOCK DIAGRAM AVDD1 AVDD2 AVDD3 AVDD4 DECAP RBIAS AGND Pro grammable Decimati.


Analog Devices AD7760

on Control Logic, I/O and Registers FIR Filter Engine VDRIVE DVDD DGND DIFF V REF+ + BUF - Multi-Bit Sigma-Delta Mo dulator Reconstruction AD7760 MCLK MCL K SYNC RESET RD/WR DRD Y CS DB0 - D B15 Figure 1. APPLICATIONS Data acqui sition systems Vibration analysis Instr umentation DataShee DataSheet4U.com PRODUCT OVERVIEW The AD7760 high perfor mance 20-bit sigma.


Analog Devices AD7760

delta analog to digital converter combi nes wide input bandwidth and high speed with the benefits of sigma delta conve rsion with performance of 100dB SNR at 2.5MSPS making it ideal for high speed data acquisition. Wide dynamic range co mbined with significantly reduced anti- aliasing requirements simplify the desi gn process. An integrated buffer to dri ve the reference, .

Part

AD7760

Description

100 dB Sigma-Delta ADC



Feature


www.DataSheet4U.com 2.5 MSPS, 20-Bit Σ ∆ ADC Preliminary Technical Data FEAT URES High performance 20-bit Sigma-Delt a ADC 118dB SNR at 78kHz output data ra te 100dB SNR at 2.5MHz output data rate 2.5 MHz maximum fully filtered output word rate Programmable over-sampling ra te (8x to 256x) Flexible parallel inter face Fully differential modulator input On-chip differential.
Manufacture

Analog Devices

Datasheet
Download AD7760 Datasheet




 AD7760
2.5 MSPS, 24-Bit, 100 dB
Sigma-Delta ADC with On-Chip Buffer
AD7760
FEATURES
120 dB dynamic range at 78 kHz output data rate
100 dB dynamic range at 2.5 MHz output data rate
112 dB SNR at 78 kHz output data rate
100 dB SNR at 2.5 MHz output data rate
2.5 MHz maximum fully filtered output word rate
Programmable oversampling rate (8× to 256×)
Fully differential modulator input
On-chip differential amplifier for signal buffering
Low-pass finite impulse response (FIR) filter with default or
user-programmable coefficients
Modulator output mode
Overrange alert bit
Digital offset and gain correction registers
Filter bypass modes
Low power and power-down modes
Synchronization of multiple devices via SYNC pin
APPLICATIONS
Data acquisition systems
Vibration analysis
Instrumentation
GENERAL DESCRIPTION
The AD7760 is a high performance, 24-bit Σ-Δ analog-to-digital
converter (ADC). It combines wide input bandwidth and high
speed with the benefits of Σ-Δ conversion to achieve a perfor-
mance of 100 dB SNR at 2.5 MSPS, making it ideal for high
speed data acquisition. Wide dynamic range combined with
significantly reduced antialiasing requirements simplify the
design process. An integrated buffer to drive the reference, a
differential amplifier for signal buffering and level shifting, an
overrange flag, internal gain and offset registers, and a low-pass
digital FIR filter make the AD7760 a compact, highly integrated
data acquisition device requiring minimal peripheral component
selection. In addition, the device offers programmable decimation
rates, and the digital FIR filter can be adjusted if the default
characteristics are not appropriate for the application. The
AD7760 is ideal for applications demanding high SNR
without a complex front-end signal processing design.
The differential input is sampled at up to 40 MSPS by an analog
modulator. The modulator output is processed by a series of low-
pass filters, with the final filter having default or user-programmable
FUNCTIONAL BLOCK DIAGRAM
VIN– VIN+
VREF+
BUF
DIFF
MCLK
SYNC
RESET
AD7760
CONTROL LOGIC
I/O
OFFSET AND GAIN
REGISTERS
MULTIBIT
Ȉ-ǻ
MODULATOR
RECONSTRUCTION
PROGRAMMABLE
DECIMATION
FIR FILTER
ENGINE
AVDD1
AVDD2
AVDD3
AVDD4
DECAPA/B
RBIAS
AGND
VDRIVE
DVDD
DGND
CS RD/WR DRDY DB0 TO DB15
Figure 1.
coefficients. The sample rate, filter corner frequencies, and output
word rate are set by a combination of the external clock frequency
and the configuration registers of the AD7760.
The reference voltage supplied to the AD7760 determines the
analog input range. With a 4 V reference, the analog input range
is ±3.2 V differential biased around a common mode of 2 V.
This common-mode biasing can be achieved using the on-chip
differential amplifier, further reducing the external signal
conditioning requirements.
The AD7760 is available in an exposed paddle, 64-lead TQFP
and is specified over the industrial temperature range from
−40°C to +85°C.
Table 1. Related Devices
Part No. Description
AD7762 24-bit, 625 kSPS, 109 dB, Σ-∆ parallel interface
AD7763 24-bit, 625 kSPS, 109 dB, Σ-∆ serial interface
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.




 AD7760
AD7760
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
Timing Specifications .................................................................. 6
Timing Diagrams.......................................................................... 7
Absolute Maximum Ratings............................................................ 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Terminology .................................................................................... 11
Typical Performance Characteristics ........................................... 12
Theory of Operation ...................................................................... 18
Modulator Data Output Mode...................................................... 19
Modulator Inputs........................................................................ 19
Modulator Data Output Scaling ............................................... 19
Modulator Data Output Mode Interface ..................................... 20
Clock Divide-by-1 Mode (CDIV = 1) ..................................... 20
Clock Divide-by-2 Mode (CDIV = 0) ..................................... 20
Using the AD7760 in Modulator Output Mode..................... 21
AD7760 Interface............................................................................ 22
Reading Data............................................................................... 22
Reading Status and Other Registers......................................... 22
Sharing the Parallel Bus ............................................................. 22
Synchronization.......................................................................... 22
Writing to the AD7760 .............................................................. 23
Clocking the AD7760 .................................................................... 24
Buffering the MCLK signal....................................................... 24
MCLK Jitter Requirements ....................................................... 24
Driving the AD7760....................................................................... 26
Using the AD7760 ...................................................................... 27
Decoupling and Layout Recommendations................................ 28
Supply Decoupling ..................................................................... 29
Additional Decoupling .............................................................. 29
Reference Voltage Filtering ....................................................... 29
Differential Amplifier Components ........................................ 29
Bias Resistor Selection ............................................................... 29
Layout Considerations............................................................... 29
Exposed Paddle........................................................................... 29
Programmable FIR Filter............................................................... 30
Downloading a User-Defined Filter ............................................ 31
Example Filter Download ......................................................... 31
AD7760 Registers ........................................................................... 33
Control Register 1—Address 0x0001 ...................................... 33
Control Register 2—Address 0x0002 ...................................... 33
Status Register (Read Only) ...................................................... 34
Offset Register—Address 0x0003............................................. 34
Gain Register—Address 0x0004............................................... 34
Overrange Register—Address 0x0005..................................... 34
Outline Dimensions ....................................................................... 35
Ordering Guide .......................................................................... 35
Rev. A | Page 2 of 36




 AD7760
REVISION HISTORY
8/06—Rev. 0 to Rev. A
Updated Package Option................................................... Universal
Change to Features............................................................................1
Changes to Specifications.................................................................4
Changes to Absolute Maximum Ratings........................................8
Changes to Terminology Section ..................................................11
Added Figure 36 Through Figure 39 ............................................17
Added Modulator Data Output Mode Section ...........................19
Added Figure 41 Through Figure 47 ............................................19
Added Modulator Data Output Mode Interface Section...........20
Changes to Reading Data Section.................................................22
Added Synchronization Section....................................................22
Changes to Clocking the AD7760 Section...................................24
Added Buffering the MCLK Signal Section.................................24
AD7760
Added MCLK Jitter Requirements Heading ...............................24
Changes to Driving the AD7760 Section.....................................26
Changes to Figure 51 ......................................................................26
Added Figure 52 ..............................................................................26
Changes to Figure 55 ......................................................................28
Changes to Figure 56 ......................................................................29
Added Exposed Paddle Section.....................................................29
Change to Control Register 2—Address 0x0002 Section ..........33
Changes to Status Register (Read Only) Section ........................34
7/05—Revision 0: Initial Version
Rev. A | Page 3 of 36






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