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KMM366S823CTF Dataheets PDF



Part Number KMM366S823CTF
Manufacturers Samsung Semiconductor
Logo Samsung Semiconductor
Description Unbuffered DIMM
Datasheet KMM366S823CTF DatasheetKMM366S823CTF Datasheet (PDF)

www.DataSheet4U.com KMM366S823CTF KMM366S823CTF SDRAM DIMM PC66 SDRAM MODULE 8Mx64 SDRAM DIMM based on 8Mx8, 4Banks, 4K Refresh, 3.3V Synchronous DRAMs with SPD GENERAL DESCRIPTION The Samsung KMM366S823CTF is a 8M bit x 64 Synchronous Dynamic RAM high density memory module. The Samsung KMM366S823CTF consists of eight CMOS 8M x 8 bit with 4banks Synchronous DRAMs in TSOP-II 400mil package and a 2K EEPROM in 8-pin TSSOP package on a 168-pin glass-epoxy substrate. Two 0.33uF decoupling capacito.

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www.DataSheet4U.com KMM366S823CTF KMM366S823CTF SDRAM DIMM PC66 SDRAM MODULE 8Mx64 SDRAM DIMM based on 8Mx8, 4Banks, 4K Refresh, 3.3V Synchronous DRAMs with SPD GENERAL DESCRIPTION The Samsung KMM366S823CTF is a 8M bit x 64 Synchronous Dynamic RAM high density memory module. The Samsung KMM366S823CTF consists of eight CMOS 8M x 8 bit with 4banks Synchronous DRAMs in TSOP-II 400mil package and a 2K EEPROM in 8-pin TSSOP package on a 168-pin glass-epoxy substrate. Two 0.33uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The KMM366S823CTF is a Dual In-line Memory Module and is intended for mounting into 168-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications. FEATURE • Performance range Part No. KMM366S823CTF-G0 • • • • • Max Freq. (Speed) 100MHz (10ns @ CL=3) Burst mode operation Auto & self refresh capability (4096 Cycles / 64ms) LVTTL compatible inputs and outputs Single 3.3V ± 0.3V power supply MRS cycle with address key programs Latency (Access from column address) Burst length (1, 2, 4, 8 & Full page) Data scramble (Sequential & Interleave) • All inputs are sampled at the positive going edge of the system clock • Serial presence detect with EEPROM • PCB : Height (1,250mil), Single sided component PIN CONFIGURATIONS (Front side/back side) Pin Front Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 VSS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VDD DQ14 DQ15 *CB0 *CB1 VSS NC NC VDD WE DQM0 Front Pin Front Pin Back VSS DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VDD DQ46 DQ47 *CB4 *CB5 VSS NC NC VDD CAS DQM4 Pin Back Pin Back 29 DQM1 57 DQ18 85 58 DQ19 86 CS0 30 87 VDD 31 DU 59 60 DQ20 88 32 VSS 61 89 NC 33 A0 62 *VREF 90 34 A2 35 A4 63 *CKE1 91 64 92 VSS 36 A6 65 DQ21 93 37 A8 38 A10/AP 66 DQ22 94 39 BA1 67 DQ23 95 68 96 VSS 40 VDD 69 DQ24 97 41 VDD 42 CLK0 70 DQ25 98 43 VSS 71 DQ26 99 72 DQ27 100 44 DU 73 VDD 101 45 CS2 46 DQM2 74 DQ28 102 47 DQM3 75 DQ29 103 76 DQ30 104 48 DU 77 DQ31 105 49 VDD 78 VSS 106 50 NC 51 79 *CLK2 107 NC NC 108 52 *CB2 80 NC 109 53 *CB3 81 82 **SDA 110 54 VSS 55 DQ16 83 **SCL 111 VDD 112 56 DQ17 84 PIN NAMES Pin Name A0 ~ A11 BA0 ~ BA1 DQ0 ~ DQ63 CLK0 ~ CLK1 CKE0 CS0, CS2 RAS CAS WE DQM0 ~ 7 VDD VSS *VREF SDA SCL SA0 ~ 2 DU NC Function Address input (Multiplexed) Select bank Data input/output Clock input Clock enable input Chip select input Row address strobe Column address strobe Write enable DQM Power supply (3.3V) Ground Power supply for reference Serial data I/O Serial clock Address in EEPROM Don′t use No connection DataSheet4U.com DQM5 141 DQ50 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 12.


KMM366S823CTS KMM366S823CTF P1014AP


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