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BT8110B Dataheets PDF



Part Number BT8110B
Manufacturers ETC
Logo ETC
Description High-Capacity ADPCM Processor
Datasheet BT8110B DatasheetBT8110B Datasheet (PDF)

www.DataSheet4U.com Bt8110/8110B High-Capacity ADPCM Processor This specification describes the Bt8110 and Bt8110B multichannel ADPCM processor CMOS integrated circuits that implement Adaptive Differential Pulse-Code Modulation (ADPCM) encoding and decoding. The fixed-rate coding algorithms include those specified in ANSI Standard T1.303-1989. These algorithms are identical to those in ITU-T Recommendations G.726 and G.727. These circuits also implement the variable-rate or embedded codes speci.

  BT8110B   BT8110B



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www.DataSheet4U.com Bt8110/8110B High-Capacity ADPCM Processor This specification describes the Bt8110 and Bt8110B multichannel ADPCM processor CMOS integrated circuits that implement Adaptive Differential Pulse-Code Modulation (ADPCM) encoding and decoding. The fixed-rate coding algorithms include those specified in ANSI Standard T1.303-1989. These algorithms are identical to those in ITU-T Recommendations G.726 and G.727. These circuits also implement the variable-rate or embedded codes specified in ANSI Standard T1.310-1991 and ITU-T Recommendation G.727. A single ADPCM processor integrated circuit can provide 24 or 32 full-duplex channels of ADPCM processing (encoding and decoding). In some applications, two circuits can be combined to provide 48 or 64 full-duplex channels. Both A-law and µ-law PCM translations are provided. Interface options such as serial and parallel inputs and outputs, along with hardware and microprocessor control modes, are provided by the integrated circuits. Up to 14 separate ADPCM algorithms are available in any given configuration on a per-channel basis. The Bt8110 requires an external lookup table ROM. The Bt8110B has an internal lookup table ROM, or can use an external lookup table ROM. When in direct framer interface mode, transparent channels in the Bt8110 will operate at 56 kbit/s; the Bt8110B operates at 64 kbit/s. A hardware control, direct framer interface mode has DataSheet4U.com been added to the Bt8110B. For more details on the Bt8110B mode controls, refer to Table 1-1 and Table 1-4. Distinguishing Features • • Bt8110B offers internal ROM 24 or 32 full-duplex channel capacity (48 or 64 channels with two processors) 2-, 3-, 4- and 5-bit quantization dynamically selectable on a channel-by-channel, frame-by-frame basis Transparent channel operation Two control modes available: microprocessor and hardware. Direct framer interface for both T1 and E1 signal formats Supports the optimal RESET function described in the algorithm standards Supports even-bit inversion of A-law inputs and outputs (required by ITU-T Recommendations G.726, and G.727) Minimum throughput delay Pin compatible with Bt8110 8 mw per-channel, low-power CMOS • • • • • • DataShee • • • Functional Block Diagram Applicable Standards • • • • • • ANSI T1.302-1987 ANSI T1.303-1989 ANSI T1.310-1991 ITU-T G.726, G.727 ANSI T1.501-1994 ANSI T1Y1 Technical Reports #3 and #10 64 Kbit/s PCM Input Convert to Uniform PCM ENCODER Input Signal + + – Difference Signal Adaptive Quantizer Signal Estimate Reconstructed Signal 32 Kbit/s ADPCM Output Adaptive Predictor + Quantized Difference Signal Inverse Adaptive Quantizer Applications • • • 64 Kbit/s PCM Output 32 Kbit/s ADPCM Input Inverse Adaptive Quantizer DECODER Quantized Difference Signal + + Reconstructed Signal Convert to PCM – Signal Estimate Synchronous Coding Adjustment Adaptive Predictor • • • • • • T1/E1 Transcoders T1/E1 Multiplexers Personal Communications Systems.


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