ISPPAC-CLK56xxA

www.DataSheet4U.com ispClock 5600A Family ™ In-System Programmable, Enhanced Zero-Delay Clock Generator with Universal Fan-Out Buffer December 2005 Preliminary Data Sheet Features ■ ■ ■ ■ 8MHz to 400MHz Input/Output Operation Low Output to Output Skew (<50ps) Low Jitter Peak-to-Peak Up to 20 Programmable Fan-out Buffers Programmable output standards and individual enable controls - LVTTL, LVCMOS, HSTL, eHSTL, SSTL, LVDS, LVPECL, Differential HSTL, SSTL Programmable output impedance - 40 to 70Ω in 5Ω increments Programmable slew rate Up to 10 banks with individual VCCO and GND - 1.5V, 1.8V, 2.5V, 3.3V ■ Up to Five Clock Frequency Domains ■ Flexible Clock Reference and External Feedback Inputs Programmable input standards - LVTTL, LVCMOS, SSTL, HSTL, LVDS, LVPECL, Differential HSTL, SSTL Clock A/B selection multiplexer Feedback A/B selection multiplexer Programmable termination ■ All Inputs and Outputs are Hot Socket Compliant ■ Four User-programmable Profiles Stored in E2CMOS® Memory Supports both test and multiple operating configurations ■ Fully Integrated High-Performance PLL Programmable lock detect Programming Support Multiply and divide ratio controlled by ■ Exceptional Power Supply Noise Immunity - Input divider (1 to 40) ■ Commercial (0 to 70°C) and Industrial - Feedback divider (1 to 40) (-40 to 85°C) Temperature Ranges - Five output dividers (2 to 80) DataSheet4U.com ■ 100-pin and 48-pin TQFP Packages Programmable on-chip loop filter Com...