Rthernet Controller. AX88796LF Datasheet

AX88796LF Controller. Datasheet pdf. Equivalent

Part AX88796LF
Description 3-in-1 Local CPU Bus Fast Rthernet Controller
Feature AX88796 L 3-in-1 Local Bus Fast Ethernet Controller 10/100BASE 3-in-1 Local CPU Bus Fast Ethernet Co.
Manufacture ASIX Electronics
Datasheet
Download AX88796LF Datasheet




AX88796LF
AX88796 L
3-in-1 Local Bus Fast Ethernet Controller
10/100BASE 3-in-1 Local CPU Bus Fast Ethernet Controller
with Embedded SRAM
Document No.: AX796-17 / V1.7 / Jan. 25 ’02
Features
Highly integrated with embedded 10/100Mbps
MAC, PHY and Transceiver
Embedded 8K * 16 bit SRAM
Compliant with IEEE 802.3/802.3u
100BASE-TX/FX specification
NE2000 register level compatible instruction
Single chip local CPU bus 10/100Mbps Fast
Ethernet MAC Controller
Support both 8 bit and 16 bit local CPU interfaces
include MCS-51 series, 80186 series and MC68K
series CPU
Support both 10Mbps and 100Mbps data rate
Support both full-duplex or half-duplex operation
Provides an extra MII port for supporting other
media. For example, Home LAN application
Support EEPROM interface to store MAC address
External and internal loop-back capability
Support Standard Print Port for printer server
application
Support upto 3/1 General Purpose In/Out pins
128-pin LQFP low profile package
Low Power Consumption, typical under 100mA
0.25 Micron low power CMOS process. 25MHz
Operation, Pure 3.3V operation with 5V I/O
tolerance.
*IEEE is a registered trademark of the Institute of
Electrical and Electronic Engineers, Inc.
*All other trademarks and registered trademark are
the property of their respective holders.
Product description
The AX88796 Fast Ethernet Controller is a high performance and highly integrated local CPU bus Ethernet Controller
with embedded 10/100Mbps PHY/Transceiver and 8K*16 bit SRAM. The AX88796 supports both 8 bit and 16 bit local
CPU interfaces include MCS-51 series, 80186 series, MC68K series CPU and ISA bus. The AX88796 implements both
10Mbps and 100Mbps Ethernet function based on IEEE802.3 / IEEE802.3u LAN standard. The AX88796 also provides
an extra IEEE802.3u compliant media-independent interface (MII) to support other media applications. Using MII
interface, Home LAN PHY type media can be supported.
As well as, the chip also provides optional Standard Print Port ( parallel port interface ), can be used for printer server
device or treat as simple general I/O port. The chip also support upto 3/1 additional General Purpose In/Out pins
System Block Diagram
AD BUS
Addr L
Addr H
Ctl BUS
AX88796
With
10/100 Mbps
PHY/TxRx
Optional Print Port
Or General I/O Ports
Optional
Home LAN
PHY
RJ11
RJ45
Always contact ASIX for possible updates before starting a design.
This data sheet contains new products information. ASIX ELECTRONICS reserves the rights to modify product specification without notice. No liability
is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
ASIX ELECTRONICS CORPORATION
First Released Date : July/31/2000
2F, NO.13, Industry East Rd. II, Science-based Industrial Park, Hsin-Chu City, Taiwan, R.O.C.
TEL: 886-3-579-9500
FAX: 886-3-579-9558
http://www.asix.com.tw



AX88796LF
AX88796 L
3-in-1 Local Bus Fast Ethernet Controller
CONTENTS
1.0 INTRODUCTION .............................................................................................................................................. 5
1.1 GENERAL DESCRIPTION:..................................................................................................................................... 5
1.2 AX88796 BLOCK DIAGRAM: .............................................................................................................................. 5
1.3A AX88796 PIN CONNECTION DIAGRAM.............................................................................................................. 6
1.3B AX88796 PIN CONNECTION DIAGRAM WITH SPP PORT OPTION ........................................................................ 7
1.3.1 AX88796 Pin Connection Diagram for ISA Bus Mode................................................................................ 8
1.3.2 AX88796 Pin Connection Diagram for 80x86 Mode................................................................................... 9
1.3.3 AX88796 Pin Connection Diagram for MC68K Mode .............................................................................. 10
1.3.4 AX88796 Pin Connection Diagram for MCS-51 Mode ............................................................................. 11
2.0 SIGNAL DESCRIPTION ................................................................................................................................. 12
2.1 LOCAL CPU BUS INTERFACE SIGNALS GROUP................................................................................................... 12
2.2 10/100MBPS TWISTED-PAIR INTERFACE PINS GROUP ......................................................................................... 13
2.3 BUILT-IN PHY LED INDICATOR PINS GROUP ..................................................................................................... 13
2.4 EEPROM SIGNALS GROUP .............................................................................................................................. 14
2.5 MII INTERFACE SIGNALS GROUP(OPTIONAL) ..................................................................................................... 14
2.6 STANDARD PRINTER PORT (SPP) INTERFACE PINS GROUP (OPTIONAL)................................................................ 15
2.7 GENERAL PURPOSE I/O PINS GROUP........................................................................................... 15
2.8 MISCELLANEOUS PINS GROUP............................................................................................................................ 16
2.9 POWER ON CONFIGURATION SETUP SIGNALS CROSS REFERENCE TABLE..................... 17
3.0 MEMORY AND I/O MAPPING...................................................................................................................... 18
3.1 EEPROM MEMORY MAPPING.......................................................................................................................... 18
3.2 I/O MAPPING................................................................................................................................................... 18
3.3 SRAM MEMORY MAPPING .............................................................................................................................. 18
4.0 BASIC OPERATION ...................................................................................................................................... 19
4.1 RECEIVER FILTERING ....................................................................................................................................... 19
4.1.1 Unicast Address Match Filter................................................................................................................... 19
4.1.2 Multicast Address Match Filter ................................................................................................................ 19
4.1.3 Broadcast Address Match Filter............................................................................................................... 20
4.1.4 Aggregate Address Filter with Receive Configuration Setup..................................................................... 20
4.2 BUFFER MANAGEMENT OPERATION .................................................................................................................. 22
4.2.1 Packet Reception ..................................................................................................................................... 22
4.2.2 Packet Transmision.................................................................................................................................. 25
4.2.3 Filling Packet to Transmit Buffer (Host fill data to memory) .................................................................... 27
4.2.4 Removing Packets from the Ring (Host read data from memory) .............................................................. 28
4.2.5 Other Useful Operations .......................................................................................................................... 31
5.0 REGISTERS OPERATION ............................................................................................................................. 32
5.1 MAC CORE REGISTERS.................................................................................................................................... 32
5.1.1 Command Register (CR) Offset 00H (Read/Write) ................................................................................... 34
5.1.2 Interrupt Status Register (ISR) Offset 07H (Read/Write).......................................................................... 34
5.1.3 Interrupt mask register (IMR) Offset 0FH (Write).................................................................................... 35
5.1.4 Data Configuration Register (DCR) Offset 0EH (Write) .......................................................................... 35
5.1.5 Transmit Configuration Register (TCR) Offset 0DH (Write) .................................................................... 35
5.1.6 Transmit Status Register (TSR) Offset 04H (Read)................................................................................... 36
5.1.7 Receive Configuration (RCR) Offset 0CH (Write).................................................................................... 36
5.1.8 Receive Status Register (RSR) Offset 0CH (Read) ................................................................................... 36
5.1.9 Inter-frame gap (IFG) Offset 16H (Read/Write)....................................................................................... 37
5.1.10 Inter-frame gap Segment 1(IFGS1) Offset 12H (Read/Write) ................................................................. 37
5.1.11 Inter-frame gap Segment 2(IFGS2) Offset 13H (Read/Write) ................................................................. 37
5.1.12 MII/EEPROM Management Register (MEMR) Offset 14H (Read/Write)................................................. 37
2 ASIX ELECTRONICS CORPORATION







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