LVDS Transmitter. CS5820 Datasheet

CS5820 Transmitter. Datasheet pdf. Equivalent

CS5820 Datasheet
Recommendation CS5820 Datasheet
Part CS5820
Description 21:3 LVDS Transmitter
Feature CS5820; www.DataSheet4U.com Myson-Century Technology GENERAL DESCRIPTION CS5820 receives three sets of 7-bi.
Manufacture Myson Technology
Datasheet
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Myson Technology CS5820
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Myson-Century Technology
CS5820
21:3 LVDS Transmitter
GENERAL DESCRIPTION
CS5820 receives three sets of 7-bit data in CMOS
logic level and convert them into three low-voltage
differential signaling (LVDS) serial channels. The 7-
bit input data is referenced to the CKIN signal. The
RF pin selects either rising or falling edge trigger of
CKIN. Parallel to serial conversion is performed by a
7X internal generated clock reference using on-chip
PLL using CKIN. A copy of CKIN but phase-locked to
the output serial streams, CLKOUT, is also
converted to the fourth LVDS channel. CS5820
offers a reliable communication media using LVDS
signaling and provides low EMI dealing with wide,
high-speed TTL interfaces.
This is especially attractive for interfaces between
GUI controller and display systems such as LCD
panels for SVGA/XGA/SXGA applications.
FEATURES
• Three 7-bit serial and one clock LVDS channels.
• Compatible with ANSI TIA/EIA-644 LVDS stan-
dard.
• Wide CKIN ranges from 31MHz to 68MHz.
• Fully integrated on-chip PLL that provides 7X
CKIN serial shift clock.
• Pin selectable for rising or falling edge trigger.
• Support power-down mode.
• 5V/3.3V tolerant data input.
• Single 3.3V supply operation.
• CMOS low power consumption.
• Functional compatible with DS90C363 and
SN75LVDS84.
• Available in 48-pin TSSOP package.
BLOCK DIAGRAM
D0-D6
D7-D13
D14-D20
RF
CKIN
SHTDN
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DIN PARALLEL-IN SERIAL-OUT
7-Bit SHIFT REGISTER
SHIFT/LOAD_N
CLK
DIN PARALLEL-IN SERIAL-OUT
7-Bit SHIFT REGISTER
SHIFT/LOAD_N
CLK
DIN PARALLEL-IN SERIAL-OUT
7-Bit SHIFT REGISTER
SHIFT/LOAD_N
CLK
7xCLK
PHASE LOCK LOOP
SHIFT/LOAD_N
R/F
CLK
CONTROL LOGIC
CS5820
Y0P
EN
Y0N
Y1P
EN
Y1N
Y2P
EN
Y2N
CKOP
EN
CKON
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Myson-Century Technology, Inc.
Taiwan:
No. 2, Industry East Rd. III,
Science-Based Industrial Park, Hsin-Chu, Taiwan
Tel: 886-3-5784866 Fax: 886-3-5784349
DataSheet4U.com
USA:
4020 Moorpark Avenue Suite
San Jose, CA, 95117
Tel: 408-243-8388 Fax: 408-243-3188
Sales@myson.com.tw
www.myson.com.tw
Rev.1.6 October 2001
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Myson Technology CS5820
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Myson-Century Technology
PIN CONNECTION DIAGRAM
CS5820
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D4
VDD
D5
D6
VSS
D7
D8
VDD
D9
D10
VSS
D11
D12
RF
D13
D14
VSS
D15
D16
D17
VDD
D18
D19
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
CS5820
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48 D3
47 D2
46 VSS
45 D1
44 D0
43 NC
42 LVDS_VSS
41 Y0N
40 Y0P
39 Y1N
38 Y1P
37 LVDS_VDD
36 LVDS_VSS
35 Y2N
34 Y2P
33 CKON
32 CKOP
31 LVDS_VSS
30 PLL_VSS
29 PLL-VDD
28 PLL_VSS
27 SHTDN
26 CKIN
25 D20
Figure-1 48-pin TSSOP
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Myson Technology CS5820
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Myson-Century Technology
CS5820
PIN DESCRIPTION
Name
I/O
D[0-6]
I
D[7-13]
D[14-20]
I
I
CKIN
I
RF I
SHTDN
Y0P,
Y0N
Y1P,
Y1N
Y2P,
Y2N
CKOP,
CKON
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PLL_VDD
PLL_VSS
LVDS_VDD
LVDS_VSS
VDD
VSS
I
O
O
O
O
P
P
P
P
P
P
Description
Parallel data input for Y0 LVDS channel. D[0] is LSB and D[6] is MSB. MSB is shifted out
first.
Parallel data input for Y1 LVDS channel. D[7] is LSB and D[13] is MSB.
Parallel data input for Y2 LVDS channel. D[14] is LSB and D[20] is MSB.
Parallel input clock.This clock signal is used for parallel data reference. It is also used by
the on-chip PLL to generate the 7X shift clock for parallel to serial conversion.
Rise/fall select. This pin selects the polarity of the CKIN edge for data input. RF = 1
selects CKIN rise edge, and RF = 0 selects CKIN fall edge.
Shutdown control (low active). When SHTDN is low, the internal PLL is put into inhibit
mode and all LVDS output channels are shut off. This also resets all internal registers.
For normal operation, SHTDN should be set to high.
Y0 LVDS channel output. These are differential LVDS outputs for Y0 channel
corresponds to D[0-6].
Y1 LVDS channel output. These are differential LVDS outputs for Y1 channel
corresponds to D[7-13].
Y2 LVDS channel output. These are differential LVDS outputs for Y2 channel
corresponds to D[14-21].
Clock LVDS channel output. These are differential LVDS output for the replica of CKIN
signal. CKOP and CKON are derived from the internal phase lock loop and phase
aligned with the serial data output and can be used by the LVDS receiver for reference
edge.
Power supply foDraPtaLLShcierceut4it.U.com
Power ground for PLL circuit.
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Power supply for output buffer circuits.
Power ground for output buffer circuits.
Power supply for internal circuits.
Power ground for internal circuits.
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