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CS5828 Dataheets PDF



Part Number CS5828
Manufacturers Myson Technology
Logo Myson Technology
Description 28:4 LVDS Transmitter
Datasheet CS5828 DatasheetCS5828 Datasheet (PDF)

www.DataSheet4U.com CS5828 28:4 LVDS Transmitter GENERAL DESCRIPTION The CS5828 receives four sets of 7-bit data in CMOS logic level and converts them into four lowvoltage differential signaling (LVDS) serial channels. The 7-bit input data is referenced to the CKIN signal. The RF pin selects either rising or falling edge trigger of CKIN. Parallel to serial conversion is performed by a 7X internal generated clock reference using onchip PLL using CKIN. A copy of CKIN but phaselocked to the output.

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www.DataSheet4U.com CS5828 28:4 LVDS Transmitter GENERAL DESCRIPTION The CS5828 receives four sets of 7-bit data in CMOS logic level and converts them into four lowvoltage differential signaling (LVDS) serial channels. The 7-bit input data is referenced to the CKIN signal. The RF pin selects either rising or falling edge trigger of CKIN. Parallel to serial conversion is performed by a 7X internal generated clock reference using onchip PLL using CKIN. A copy of CKIN but phaselocked to the output serial streams, CLKOUT, is also converted to the fifth LVDS channel. The CS5828 offers a reliable communication media using LVDS signaling and provides low EMI dealing with wide, high-speed TTL interfaces. This is especially attractive for interfaces between GUI controller and display systems such as LCD panels for SVGA/XGA/SXGA applications. FEATURES • Four 7-bit serial and one clock LVDS channels. • Compatible with ANSI TIA/EIA-644 LVDS standard. • Wide CKIN ranges from 31MHz to 85MHz. • Fully integrated on-chip PLL that provides 7X CKIN serial shift clock. • Pin selectable for rising or falling edge trigger. • Support power-down mode. • 5V/3.3V tolerant data input. • Single 3.3V supply operation. • CMOS low power consumption. • Functional compatible with DS90C385. • Available in 56-pin TSSOP package. BLOCK DIAGRAM D0,D1,D2,D3, D4,D6,D7 DIN DataSheet4U.com DataShee SHIFT/LOAD_N CLK PARALLEL-IN SERIAL-OUT 7-Bit SHIFT REGISTER Y0P EN Y0N D8,D9,D12,D13, D14,D15,D18 DIN SHIFT/LOAD_N CLK PARALLEL-IN SERIAL-OUT 7-Bit SHIFT REGISTER Y1P EN Y1N D19,D20,D21,D22, D24,D25,D26 DIN PARALLEL-IN SERIAL-OUT EN Y2P Y2N SHIFT/LOAD_N 7-Bit SHIFT REGISTER CLK D27,D5,D10,D11, D16,D17,D23 DIN SHIFT/LOAD_N CLK PARALLEL-IN SERIAL-OUT 7-Bit SHIFT REGISTER Y3P EN Y3N RF CKIN 7xCLK PHASE LOCK LOOP SHIFT/LOAD_N R/F CLK CKOP EN CKON SHTDN CONTROL LOGIC CS5828 Myson Century, Inc. Taiwan: No. 2, Industry East Rd. III, Science-Based Industrial Park, Hsin-Chu, Taiwan DataSheet4U.com Tel: 886-3-5784866 Fax: 886-3-5784349 USA: 4020 Moorpark Avenue Suite 115 San Jose, CA, 95117 Tel: 408-243-8388 Fax: 408-243-3188 [email protected] www.myson.com.tw Rev.1.4 August 2002 page 1 of 13 DataSheet4U.com DataSheet 4 U .com www.DataSheet4U.com CS5828 PIN CONNECTION DIAGRAM VDD D5 D6 D7 VSS D8 D9 D10 VDD D11 D12 D13 VSS D14 D15 D16 RF D17 D18 D19 VSS D20 D21 D22 D23 VDD D24 D25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 D4 D3 D2 VSS D1 D0 D27 LVDS_VSS Y0M Y0P Y1M Y1P LVDS_VDD LVDS_VSS Y2M Y2P CKOM CKOP Y3M Y3P LVDS_VSS PLL_VSS PLL_VDD PLL_VSS SHTDN CKIN D26 VSS CS5828 et4U.com DataSheet4U.com 36 35 34 33 32 31 30 29 DataShee Figure-1 56-pin TSSOP page 2 of 13 DataSheet4U.com DataSheet4U.com DataSheet 4 U .com www.DataSheet4U.com CS5828 PIN DESCRIPTION Name D0,D1,D2,D3,D4, D6,D7 D8,D9,D12,D13, D14,D15,D18 D19,D20,D21,D22 ,D24,D25,D26 D27,D5,D10,D11, D16,D17,D23 CKIN RF SHTDN I/O I I I I I I I Description Parallel data input for Y0 LVDS channel. D[0] is LSB and D[7] is MSB. MSB is shifted out first. Parallel data input for Y1 LVDS channel. D[8] is LSB and D[18] is MSB. Parallel data input for Y2 LVDS channel. D[19] is LSB and D[26] is MSB. Parallel data input for Y3 LVDS channel. D[27] is LSB and D[23] is MSB. Parallel input clock.This clock signal is used for parallel data reference. It is also used by the on-chip PLL to generate the 7X shift clock for parallel to serial conversion. Rise/fall select. This pin selects the polarity of the CKIN edge for data input. RF = 1 selects CKIN rise edge, and RF = 0 selects CKIN fall edge. Shutdown control (low active). When SHTDN is low, the internal PLL is put into inhibit mode and all LVDS output channels are shut off. This also resets all internal registers. For normal operation, SHTDN should be set to high. Y0 LVDS channel output. These are differential LVDS outputs for Y0 channel corresponds to D0, D1, D2, D3, D4, D6, D7. Y1 LVDS channel output. These are differential LVDS outputs for Y1 channel corresponds to D8, D9, D12, D13, D14, D15, D18. Y2 LVDS channel output. These are differential LVDS outputs for Y2 channel corresponds to D19, D20, D21,D22, D24, D25, D26. Y3 LVDS channel output. These are differential LVDS outputs for Y3 channel corresponds to D27, D5, D10, D11, D16, D17, D23. Clock LVDS channel output. These are differential LVDS output for the replica of CKIN signal. CKOP and CKON are derived from the internal phase lock loop and phase aligned with the serial data output and can be used by the LVDS receiver for reference edge. Power supply for PLL circuit. Power ground for PLL circuit. Power supply for output buffer circuits. Power ground for output buffer circuits. Power supply for internal circuits. Power ground for internal circuits. Y0P, Y0N Y1P, Y1N Y2P, Y2N Y3P, Y3N CKOP, CKON O O O O O et4U.com DataSheet4U.com DataShee PLL_VDD PLL_VSS LVDS_VDD LVDS_VSS VD.


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