HY57V643220D

www.DataSheet4U.com HY57V643220D(L/S)T(P) Series 4Banks x 512K x 32bits Synchronous DRAM Document Title 4Bank x 512K x 32bits Synchronous DRAM Revision History Revision No. 0.1 0.2 0.3 0.4 Initial Draft Removed Preliminary 1. Updated Output Load Capacitance for Access Time Measurement CL = 30pF in AC OPERATING TEST CONDITION 2. Updated the tolerance zone of the leads and the description of the package type in PACKAGE DIMENSION 1.Corrected : Lead range tolerance (Page : 13) History Draft Date May. 2004 July 2004 Sep. 2004 Sep. 2005 Remark Preliminary DataSheet4U.com DataShee This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.4 / Sep. 2005 1 DataSheet4U.com DataSheet4U.com DataSheet 4 U .com www.DataSheet4U.com HY57V643220D(L/S)T(P) Series 4Banks x 512K x 32bits Synchronous DRAM DESCRIPTION The Hynix HY57V643220D(L/S)T(P) series is a 67,108,864bit CMOS Synchronous DRAM, ideally suited for the memory applications which require wide data I/O and high bandwidth. HY57V643220D(L/S)T(P) is organized as 4banks of 524,228x32. HY57V643220D(L/S)T(P) is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatibl...