8-bit Microcontroller. AT89LP214 Datasheet

AT89LP214 Datasheet PDF, Equivalent


Part Number

AT89LP214

Description

8-bit Microcontroller

Manufacture

ATMEL Corporation

Total Page 30 Pages
PDF Download
Download AT89LP214 Datasheet PDF


AT89LP214 Datasheet
Features
8-bit Microcontroller Compatible with MCS®51 Products
Enhanced 8051 Architecture
– Single Clock Cycle per Byte Fetch
– Up to 20 MIPS Throughput at 20 MHz Clock Frequency
– Fully Static Operation: 0 Hz to 20 MHz
– On-chip 2-cycle Hardware Multiplier
– 128 x 8 Internal RAM
– 4-level Interrupt Priority
Nonvolatile Program Memory
– 2K Bytes of In-System Programmable (ISP) Flash Memory
– Endurance: Minimum 10,000 Write/Erase Cycles
– Serial Interface for Program Downloading
– 32-byte Fast Page Programming Mode
– 64-byte User Signature Array
– 2-level Program Memory Lock for Software Security
Peripheral Features
– Two 16-bit Enhanced Timer/Counters
– Two 8-bit PWM Outputs (AT89LP213 Only)
– Enhanced UART with Automatic Address Recognition and Framing Error
Detection (AT89LP214 Only)
– Enhanced Master/Slave SPI with Double-buffered Send/Receive
– Programmable Watchdog Timer with Software Reset
– Analog Comparator with Selectable Interrupt and Debouncing
– 8 General-purpose Interrupt Pins
Special Microcontroller Features
– Two-wire On-chip Debug Interface
– Brown-out Detection and Power-on Reset with Power-off Flag
– Internal 8 MHz RC Oscillator
– Low Power Idle and Power-down Modes
– Interrupt Recovery from Power-down Mode
I/O and Packages
– Up to 12 Programmable I/O Lines
– Configurable I/O with Quasi-bidirectional, Input, Push-pull Output, and
Open-drain Modes
– 5V Tolerant I/O
– 14-lead TSSOP or PDIP
Operating Conditions
– 2.4V to 5.5V VCC Voltage Range
– -40° C to 85°C Temperature Range
8-bit
Microcontroller
with 2K Bytes
Flash
AT89LP213
AT89LP214
1. Description
The AT89LP213/214 is a low-power, high-performance CMOS 8-bit microcontroller
with 2K bytes of In-System Programmable Flash memory. The device is manufactured
using Atmel's high-density nonvolatile memory technology and is compatible with the
industry-standard MCS-51 instruction set. The AT89LP213/214 is built around an
enhanced CPU core that can fetch a single byte from memory every clock cycle.
In the classic 8051 architecture, each fetch requires 6 clock cycles, forcing instruc-
tions to execute in 12, 24 or 48 clock cycles. In the AT89LP213/214 CPU, instructions
3538E–MICRO–11/10

AT89LP214 Datasheet
need only 1 to 4 clock cycles providing 6 to 12 times more throughput than the standard 8051.
Seventy percent of instructions need only as many clock cycles as they have bytes to execute,
and most of the remaining instructions require only one additional clock. The enhanced CPU
core is capable of 20 MIPS throughput whereas the classic 8051 CPU can deliver only 4 MIPS
at the same current consumption. Conversely, at the same throughput as the classic 8051, the
new CPU core runs at a much lower speed and thereby greatly reduces power consumption.
The AT89LP213/214 provides the following standard features: 2K bytes of In-System Program-
mable Flash memory, 128 bytes of RAM, up to 12 I/O lines, two 16-bit timer/counters, two PWM
outputs (AT89LP213 only), a programmable watchdog timer, a full duplex serial port
(AT89LP214 only), a serial peripheral interface, an internal 8 MHz RC oscillator, on-chip crystal
oscillator, and a four-level, six-vector interrupt system.
The two timer/counters in the AT89LP213/214 are enhanced with two new modes. Mode 0 can
be configured as a variable 9- to 16-bit timer/counter and Mode 1 can be configured as a 16-bit
auto-reload timer/counter. In addition, the timer/counters on the AT89LP213 may independently
drive a pulse width modulation output.
The I/O ports of the AT89LP213/214 can be independently configured in one of four operating
modes. In quasi-bidirectional mode, the ports operate as in the classic 8051. In input mode, the
ports are tristated. Push-pull output mode provides full CMOS drivers and open-drain mode pro-
vides just a pull-down. In addition, all 8 pins of Port 1 can be configured to generate an interrupt
using the general-purpose interrupt interface. The I/O pins of the AT89LP213/214 tolerate volt-
ages higher than the device’s own power supply, up to 5.5V. When the device is supplied at
2.4V and all I/O ports receive 5.5V, the total back flowing current in all I/Os is less than 100 µA.
2. Pin Configuration
2.1 AT89LP213: 14-lead TSSOP/PDIP
(GPI5/MOSI) P1.5
(GPI7/SCK) P1.7
(GPI5/RST) P1.3
GND
(GPI2) P1.2
(T0) P3.4
(INT0/XTAL1) P3.2
1
2
3
4
5
6
7
14 P1.6 (MISO/GPI6)
13 P1.4 (SS/GPI4)
12 P1.1 (AIN1/GPI1)
11 P1.0 (AIN0/GPI0)
10 VCC
9 P3.5 (T1)
8 P3.3 (XTAL2/CLKOUT/INT1)
2.2 AT89LP214: 14-lead TSSOP/PDIP
(GPI5/MOSI) P1.5
(GPI7/SCK) P1.7
(GPI5/RST) P1.3
GND
(GPI2) P1.2
(RxD) P3.0
(INT0/XTAL1) P3.2
1
2
3
4
5
6
7
14 P1.6 (MISO/GPI6)
13 P1.4 (SS/GPI4)
12 P1.1 (AIN1/GPI1)
11 P1.0 (AIN0/GPI0)
10 VCC
9 P3.1 (TxD)
8 P3.3 (XTAL2/CLKOUT/INT1)
2 AT89LP213/214
3538E–MICRO–11/10


Features Datasheet pdf Features • 8-bit Microcontroller Compa tible with MCS®51 Products • Enhance d 8051 Architecture – Single Clock Cy cle per Byte Fetch – Up to 20 MIPS Th roughput at 20 MHz Clock Frequency – Fully Static Operation: 0 Hz to 20 MHz – On-chip 2-cycle Hardware Multiplier – 128 x 8 Internal RAM – 4-level I nterrupt Priority • Nonvolatile Progr am Memory – 2K Bytes of In-System Pro grammable (ISP) Flash Memory – Endura nce: Minimum 10,000 Write/Erase Cycles – Serial Interface for Program Downlo ading – 32-byte Fast Page Programming Mode – 64-byte User Signature Array – 2-level Program Memory Lock for Sof tware Security • Peripheral Features – Two 16-bit Enhanced Timer/Counters – Two 8-bit PWM Outputs (AT89LP213 On ly) – Enhanced UART with Automatic Ad dress Recognition and Framing Error Det ection (AT89LP214 Only) – Enhanced Ma ster/Slave SPI with Double-buffered Sen d/Receive – Programmable Watchdog Tim er with Software Reset – Analog Comparator with Selectable Interrupt and Debouncing – 8 General-purpose In.
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