MX23L6412

www.DataSheet4U.com MX23L6412 SEQUENTIAL 64M-BIT MASK ROM FEATURES Bit organization - 4M x 16 (word mode only) - 256 words/page - Total 16K pages Sequential access at 200ns cycle time in a page Asynchronous chip enable input (ALEH, ALEL) Access time - Read latency time: 950ns - Read cycle time: 200ns - RD access time: 150ns Current - Operating:25mA(max.) - Address input:2mA(max.) - Standby:20uA(max.) Supply voltage - 3.0V~3.6V Package - 32 pin TSOP ORDER INFORMATION Part No. MX23L6412TC-20 Read Cycle Time 200ns Package 32 pin TSOP DataShee DataSheet4U.com GENERAL DESCRIPTION The product is a 64M bits (4M x 16) mask ROM composed of 16K pages, and each consists of 256 words memory cell array. This mask ROM has a 16 bit address input / data output bus (AD0~AD15), two address latch enable pins (high : ALEH, low : ALEL), a read strobe (RD). There are 3 modes, Stand-by mode, Active mode, and Address input mode. Stand-by mode is a non-operating state, and has the smallest current dissipation. Active mode is an operating state, and data output is possible. Address input mode is a state of address input. Address input is through AD bus when ALEL is high. The high and low 16 bit addresses are latched at ALEH’sand ALEL falling edges. As for high 16 bit address, A0~A6 are through 7 bit address register, A7~A15 are not used internally. As for low 16 bit address, A1~A8 are through 8 bit address counter, A9~A15 are through 7 bit address register, and A0 are not used inter...