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DATA SHEET
MOS FIELD EFFECT TRANSISTOR
NP34N055HHE, NP34N055IHE
SWITCHING N-CHANNEL POWER MOS FET INDUSTRIAL USE
ORDERING INFORMATION
PART NUMBER NP34N055HHE NP34N055IHE PACKAGE TO-251 TO-252
DESCRIPTION
These products are N-Channel MOS Field Effect Transistors designed for high current switching applications.
FEATURES
• Channel temperature 175 degree rated • Super low on-state resistance RDS(on) = 19 m Ω MAX. (VGS = 10 V, I D = 17 A) • Low Ciss : Ciss = 1600 pF TYP. • Built-in gate protection diode
ABSOLUTE MAXIMUM RATINGS (T A = 25 °C)
Drain to Source Voltage Gate to Source Voltage Drain Current (DC) Drain Current (Pulse)
Note1
(TO-251) 55 ±20 ±34 V V A A W W A mJ °C °C (TO-252)
VDSS VGSS ID(DC) ID(pulse) PT PT IAS EAS Tch Tstg
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±136 1.2 88 34 / 27 / 10 11 / 72 / 100 175 –55 to + 175
Total Power Dissipation (TA = 25 °C) Total Power Dissipation (TC = 25 °C) Single Avalanche Current Single Avalanche Energy Channel Temperature Storage Temperature Notes 1. PW ≤ 10 µ s, Duty cycle ≤ 1 %
Note2 Note2
2. Starting Tch = 25 °C, RG = 25 Ω, VGS = 20 V → 0 V (see Figure 4.)
THERMAL RESISTANCE
Channel to Case Channel to Ambient Rth(ch-C) Rth(ch-A) 1.70 125 °C/W °C/W
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The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. D14153EJ3V0DS00 (3rd edition) Date Published March 2001 NS CP(K) Printed in Japan
The mark 5 shows major revised points.
©
1999,2000
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NP34N055HHE, NP34N055IHE
ELECTRICAL CHARACTERISTICS (T A = 25 °C)
CHARACTERISTICS Drain to Source On-state Resistance Gate to Source Threshold Voltage Forward Transfer Admittance Drain Leakage Current Gate to Source Leakage Current Input Capacitance Output Capacitance Reverse Transfer Capacitance Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Total Gate Charge Gate to Source Charge Gate to Drain Charge Body Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge SYMBOL RDS(on) VGS(th) | yfs | IDSS IGSS Ciss Coss Crss td(on) tr td(off) tf QG QGS QGD VF(S-D) trr Qrr TEST CONDITIONS VGS = 10 V, ID = 17 A VDS = VGS, ID = 250 µ A VDS = 10 V, ID = 17 A VDS = 55 V, VGS = 0 V VGS = ±20 V, VDS = 0 V VDS = 25 V VGS = 0 V f = 1 MHz ID = 17 A VGS(on) = 10 V VDD = 28 V RG = 1 Ω ID = 34 A VDD = 44 V VGS = 10 V IF = 34 A, VGS = 0 V IF = 34 A, VGS = 0 V di/dt = 100 A/µ s 1600 250 120 21 15 35 12 30 9 12 1.0 40 58 2.0 6 MIN. TYP. 15 3.0 12 10 ±10 2400 380 220 47 38 70 29 45 MAX. 19 4.0 UNIT mΩ V S
µA µA
pF pF pF ns ns ns ns nC nC nC V ns nC
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TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
TEST CIRCUIT 1 AVALANCHE CAPABILITY
D.U.T. RG = 25 Ω PG. VGS = 20 → 0 V 50 Ω
L VDD PG. RG
VGS RL VDD VDS
90 % 90 % 10 % 10 %
VGS
Wav.
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