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KS8803B
10/15 CH PLL
INTRODUCTION
16-DIP-300A The KS8803B/4B are designed to select 10/15 channels of cordlss phone of which frequency band is 46/49MHz. It has reference frequency generator, programmable divider for transmit and receive section and phase detector.
16-SOP-225
FEATURES
• 10 Channels selectable : KS8803B (both transmit/receive) • 15 Channels selectable : KS8804B (both transmit/receive) • Include oscillation circuit with external x-tal (10.24MHz) • 5KHz output for guard tone • Unlock detector (phase difference more than 6.25us) • Stand-by function for power saving
ORDERING INFORMATION
Device KS8803B KS8803BD Package 16-DIP-300A 16-SOP-225 Operating Temperature - 30°C ~ + 75°C
BLOCK DIAGRAM
VDD
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VS S
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+V
DD
15
12 4
F1
OSC IN
16 1 11
PHASE DETECTOR (Tx)
REFERENCE DIVIDER
OSC OUT
PDT
PHASE DETECTOR (Rx)
13
PDR
TIF
9
PROGRAMMABLE DIVIDER (Tx)
PR OGRAMMABLE DIVIDER (Rx)
14
+
RIF
DECODER
UNLOCK DETECTOR
10
LDT
3
SB
5
D0
6
D1
7
D2
8
2
D3 MODE
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KS8803B
10/15 CH PLL
PIN CONFIGURATION
OSC OUT
1 2 3 4 KS8803B 5 6 7 8
16 15 14 13 12 11 10 9
OSC IN
MODE
V DD
SB
RIF
F1
PDR
D0
VS S PDT
D1
D2
LDT
D3
TIF
PIN DESCRIPTION
Pin No Symbol Description •This output generates reference frequency 1 OSC OUT when it is connected to Pin 16 with external OSC of which frequency is 10.24MHz • Base/Remote Unit Selection Pin 2 MODE “High” : Base Unit “Low” : Remote Unit • Stand-by pin
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3 SB
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• This input controls Tx PLL for reducing the power dissipation “High” : Normal operation “Low” : Stand-by 4 5 6 7 8 F1 D0 D1 D2 D3 • Input to programmable divider of Tx 9 TIF • AC coupling with VCO • In case of lager signal, It needs DC-coupling • Min. input voltage is 0.1Vrms 10 LDT • Unlocked signal out pin (see output charateristics) • 5KHz output • Channel selection pins • The Combinations of these inputs select one channel among the 10/15 channels
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KS8803B
10/15 CH PLL
PIN DESCRIPTION
Pin No Symbol • Phase detector output for Tx 11 PDT • PDT detects the phase error from Tx PLL and its output is connected to external low pass filter 12 VSS • This pin is negative supply of the IC. • It usually grounded • Phase detector output for Rx 13 PDR • PDR detects the phase error from Rx PLL and its output is connected to external low pass filter • Input of programmable divider for Rx. • AC coupling with VCO 14 RIF • In case of lager signal (standard CMOS logic), it needs DC coupling • Min. input voltage is 0.1Vrms • This pin is positive supply of the IC 15 VDD • Its reference is VSS, and normally + 3.0V ~ + 5.5V more positive than VSS • X-TAL osc connection pin 16 OSC IN Description
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DataSheet4U.com • This input generates the reference frequency
when it is connected to pin 1 with external osc
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