Document
CXD2498R
Timing Generator for Frame Readout CCD Image Sensor
Description The CXD2498R is a timing generator IC which generates the timing pulses for performing frame readout using the ICX282 CCD image sensor. Features • Base oscillation frequency 45MHz • Electronic shutter function • Supports various drive modes such as draft and AF mode • Horizontal driver for CCD image sensor • Vertical driver for CCD image sensor Applications Digital still cameras Structure Silicon gate CMOS IC Applicable CCD Image Sensors ICX282 (Type 2/3, 5070K pixels) 48 pin LQFP (Plastic)
Absolute Maximum Ratings • Supply voltage VDD VSS – 0.3 to +7.0 V VL –10.0 to VSS V VH VL – 0.3 to +26.0 V • Input voltage VI VSS – 0.3 to VDD + 0.3 V • Output voltage VO1 VSS – 0.3 to VDD + 0.3 V VO2 VL – 0.3 to VSS + 0.3 V VO3 VL – 0.3 to VH + 0.3 V • Operating temperature Topr –20 to +75 °C • Storage temperature Tstg –55 to +150 °C Recommended Operating Conditions • Supply voltage VDDa, VDDb, VDDc 3.0 to 3.6 VM 0.0 VH 14.5 to 15.5 VL –7.0 to –8.0 • Operating temperature Topr –20 to +75
V V V V °C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E00X63-PS
CXD2498R
Block Diagram
VDD2
VDD3
H1A
H1B
H2A
8
11 16 10 12 13 15
H2B
RG
9
14
18 19
VCO
XSHD
XSHP
VSS2
VSS3
17 VDD4 20 PBLK CKI 21 CLPDM 26 Pulse Generator 1/2 22 OBCLP 23 ADCLK 24 VSS4 4 5 ID/EXP WEN
CKO 25 MCKO 30
SNCSL
3
Selector
Latch
40 V1A 42 V1B 43 V1C
SSI 31 SCK 32 SEN 33
Selector
Register
38 V2 44 V3A 46 V3B V Driver 47 V3C 39 V4 48 SUB 41 VH 37 VM 45 VL
SSGSL
6 SSG
RST
2
TEST1 27 TEST2 28
7
VDD1
29
VDD5
1
VSS1
36
VSS5
35
HD
34
VD
–2–
CXD2498R
Pin Configuration
TEST2
MCKO
VSS5
TEST1
VDD5
SEN
SCK
SSI
HD
VD
36 VM V2 V4 V1A VH V1B V1C V3A VL V3B V3C SUB 37 38 39 40 41 42 43 44 45 46 47 48 1
35
34
33
32
31
30
29
28
27
26
25 24 VSS4 23 ADCLK 22 OBCLP 21 CLPDM 20 PBLK 19 XSHD 18 XSHP 17 VDD4 16 VDD3 15 H2B 14 VSS3 13 H2A
2
3
4
5
6
7
8
9
10
11
12
VDD1
SNCSL
ID/EXP
WEN
VSS1
VSS2
RST
VDD2
SSGSL
∗ Groups of pins enclosed in the figure indicate sections for which power supply separation is possible.
–3–
H1A
H1B
RG
CKO
CKI
CXD2498R
Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Symbol VSS1 RST SNCSL ID/EXP WEN SSGSL VDD1 RG VSS2 H1A VDD2 H1B H2A VSS3 H2B VDD3 VDD4 XSHP XSHD PBLK CLPDM OBCLP ADCLK VSS4 CKO CKI TEST1 TEST2 VDD5 MCKO SSI I/O — I I O O I — O — O — O O — O — — O O O O O O — O I I I — O I GND Internal system reset input. High: Normal operation, Low: Reset control Normally apply reset during power-on. Schmitt trigger input Control input used to switch sync system. High: CKI sync, Low: MCKO sync With pull-down resistor Description
Vertical direction line identification pulse output/exposure time identification pulse output. Switching possible using the serial interface data. (Default: ID) Memory write timing pulse output. Internal SSG enable. High: Internal SSG valid, Low: External sync valid With pull-down resistor
3.3V power supply. (Power supply for common logic block) CCD reset gate pulse output. GND CCD horizontal register clock output. 3.3V power supply. (Power supply for H block) CCD horizontal register clock output. CCD horizontal register clock output. GND CCD horizontal register clock output. 3.3V power supply. (Power supply for H block) 3.3V power supply. (Power supply for CDS block) CCD precharge level sample-and-hold pulse output. CCD data level sample-and-hold pulse output. Pulse output for horizontal and vertical blanking period pulse cleaning. CCD dummy signal clamp pulse output. CCD optical black signal clamp pulse output. The horizontal OB pattern can be changed using the serial interface data. Clock output for analog/digital conversion IC. Logical phase adjustment possible using the serial interface data. GND Inverter output. Inverter input. IC test pin 1; normally fixed to GND. IC test pin 2; normally fixed to GND. 3.3V power supply. (Power supply for common logic block) System clock output for signal processing IC. Serial interface data input for internal mode settings. Schmitt trigger input –4– With pull-down resistor With pull-down resistor
CXD2498R
Pin No. 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
Symbol SCK SEN VD HD VSS5 VM V2 V4 V1A VH V1B V1C V3A VL V3B V3C SUB
I/O I I I/O I/O — — O O O — O O O — O O O
Description Serial interface clock input for internal mode settings. Schmitt trigger input Serial interface strobe input for internal mode settings. Schmitt trigger input Vertical sync signal input/output. Horizontal sync signal input/output. GND GND (GND fo.