Flash Memory/SRAM. AM41DL32X4G Datasheet

AM41DL32X4G Memory/SRAM. Datasheet pdf. Equivalent

Part AM41DL32X4G
Description Stacked Multi-Chip Package (MCP) Flash Memory/SRAM
Feature www.DataSheet4U.com Am41DL32x4G Data Sheet July 2003 The following document specifies Spansion mem.
Manufacture SPANSION
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Data Sheet
July 2003
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-
inally developed the specification, these products will be offered to customers of both AMD and
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order
these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
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Publication Number 25559 Revision A Amendment 0 Issue Date November 12, 2001

Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash
Memory and 4 Mbit (512 K x 8-Bit/256 K x 16-Bit) Static RAM
MCP Features
s Power supply voltage of 2.7 to 3.3 volt
s High performance
— Access time as fast as 70 ns
s Package
— 73-Ball FBGA
s Operating Temperature
— –40°C to +85°C
s Data Management Software (DMS)
AMD-supplied software manages data programming and
erasing, enabling EEPROM emulation
Eases sector erase limitations
s Supports Common Flash Memory Interface (CFI)
s Erase Suspend/Erase Resume
Suspends erase operations to allow programming in same
Flash Memory Features
s Data# Polling and Toggle Bits
Provides a software method of detecting the status of
s Simultaneous Read/Write operations
— Data can be continuously read from one bank while
executing erase/program functions in other bank
program or erase cycles
s Unlock Bypass Program command
Reduces overall programming time when issuing multiple
program command sequences
— Zero latency between read and write operations
s Secured Silicon (SecSi) Sector: Extra 256 Byte seDctaortaSheet4sU.cAonmy combination of sectors can be erased
Factory locked and identifiable: 16 bytes available for
secure, random factory Electronic Serial Number; verifiable
s Ready/Busy# output (RY/BY#)
as factory locked through autoselect function.
Hardware method for detecting program or erase cycle
Customer lockable: Sector is one-time programmable. Once
locked, data cannot be changed
s Hardware reset pin (RESET#)
s Zero Power Operation
— Sophisticated power management circuits reduce power
Hardware method of resetting the internal state machine to
reading array data
consumed during inactive periods to nearly zero
s WP#/ACC input pin
s Top or bottom boot block
s Manufactured on 0.17 µm process technology
s Compatible with JEDEC standards
Pinout and software compatible with single-power-supply
flash standard
Write protect (WP#) function allows protection of two outermost
boot sectors, regardless of sector protect status
Acceleration (ACC) function accelerates program timing
s Sector protection
Hardware method of locking a sector, either in-system or
using programming equipment, to prevent any program or
s High performance
Access time as fast as 70 ns
erase operation within that sector
Temporary Sector Unprotect allows changing data in
protected sectors in-system
Program time: 4 µs/word typical utilizing Accelerate function
SRAM Features
s Ultra low power consumption (typical values)
2 mA active read current at 1 MHz
10 mA active read current at 5 MHz
200 nA in standby or automatic sleep mode
s Minimum 1 million write cycles guaranteed per sector
s 20 Year data retention at 125°C
Reliable operation for the life of the system
s Power dissipation
Operating: 22 mA maximum
Standby: 10 µA maximum
s CE1s# and CE2s Chip Select
s Power down features using CE1s# and CE2s
s Data retention supply voltage: 1.5 to 3.3 volt
s Byte data control: LB#s (DQ7–DQ0), UB#s (DQ15–DQ8)
This document contains information on a product under development at Advanced Micro Devices. The information
Publication# 25559 Rev: A Amendment/0
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
Issue Date: November 12, 2001
product without notice.
Refer to AMD’s Website (www.amd.com) for the latest information.
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