AS4LC1M16S1

www.DataSheet4U.com May 2001 Preliminary ® 3.3V 2M × 8/1M × 16 CMOS synchronous DRAM Features Organization - 1,048,576 words × 8 bits × 2 banks (2M × 8) 11 row, 9 column address - 524,288 words × 16 bits × 2 banks (1M × 16) 11 row, 8 column address AS4LC2M8S1 AS4LC2M8S0 AS4LC1M16S1 AS4LC1M16S0 All signals referenced to positive edge of clock, fully synchronous Dual internal banks controlled by A11 (bank select) High speed - 143/125/100 MHz - 7/8/10 ns clock access time Auto refresh and self refresh PC100 functionality Automatic and direct precharge including concurrent autoprecharge Burst read, write/Single write Random column address assertion in every cycle, pipelined operation LVTTL compatible I/O 3.3V power supply JEDEC standard package, pinout and function - 400 mil, 44-pin TSOP 2 (2M × 8) - 400 mil, 50-pin TSOP 2 (1M × 16) Low power consumption - Active: 576 mW max - Standby: 7.2 mW max, CMOS I/O 2048 refresh cycles, 32 ms refresh interval 4096 refresh cycles, 64 ms refresh interval Read/write data masking Programmable burst length (1/2/4/8/ full page) Programmable burst sequence (sequential/interleaved) Programmable CAS latency (1/2/3) Pin arrangement TSOP 2 VCC DQ0 VSSQ DQ1 VCCQ DQ2 VSSQ DQ3 VCCQ NC NC WE CAS RAS CS A11 A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 VSS DQ7 VSSQ DQ6 VCCQ DQ5 VSSQ DQ4 VCCQ NC NC DQM CLK CKE NC A...