UG516W724(8)4HK(S)G - DRAM
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UG516W724(8)4HK(S)G
Revision History
Jan 11 , 2000 Rev - B May 05 , 1999 Rev - A
Added More Detai...
Description
www.DataSheet4U.com
UG516W724(8)4HK(S)G
Revision History
Jan 11 , 2000 Rev - B May 05 , 1999 Rev - A
Added More Detailed Dimension Information Of PCB , Full Data sheet Changed to new format. Datasheet released.
DataShee
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UG516W724(8)4HK(S)G
128M Bytes (16M x 72) DRAM 168Pin DIMM With ECC based on 16M x 4 General Description
The UG516W724(8)4HK(S)G is a 16,7774,216 bits by 72 EDO DRAM module with ECC . The UG516W724(8)4HK(S)G is assembled using 18 pcs of 16Mx4 4K\8K refresh DRAMs in 32-pin SOJ/TSOP package,and 2 pcs ABT163244 buffers in 240mil package mounted on a 168-pin buffered printed circuit board.
Features
Single 3.3 +/- 0.3V power supply Extended data out mode CAS-before-RAS Refresh capability RAS-only and Hidden Refresh capability 4096 \ 8192 refresh cycles every 64 \ 128 ms 12/12 \ 13/11 Addressing (Row / Column) LVTTL compatible inputs and output Buffered input except RAS and DQ New JEDEC standard pinout & Buffered PDpin PCB:Height (1250mil),double sided component
Pin Assignment
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Signal VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 DQ16 DQ17 VSS NC NC VCC WE0 CAS0 NC RAS0 OE0 VSS A0 A2 A4 A6 A...
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