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NT5DS64M4AW Dataheets PDF



Part Number NT5DS64M4AW
Manufacturers Nanya
Logo Nanya
Description (NT5DSxxMxAx) 256Mb DDR333/300 SDRAM
Datasheet NT5DS64M4AW DatasheetNT5DS64M4AW Datasheet (PDF)

www.DataSheet4U.com NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW 256Mb DDR333/300 SDRAM Features CAS Latency and Frequency CAS Latency 2 2.5 Maximum Operating Frequency (MHz)* DDR333 (-6) DDR300 (-66) 133 133 166 150 • Double data rate architecture: two data transfers per clock cycle • Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver • DQS is edge-aligned with data for reads and is centeraligned with data for writes • Diffe.

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www.DataSheet4U.com NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW 256Mb DDR333/300 SDRAM Features CAS Latency and Frequency CAS Latency 2 2.5 Maximum Operating Frequency (MHz)* DDR333 (-6) DDR300 (-66) 133 133 166 150 • Double data rate architecture: two data transfers per clock cycle • Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver • DQS is edge-aligned with data for reads and is centeraligned with data for writes • Differential clock inputs (CK and CK) • Four internal banks for concurrent operation • Data mask (DM) for write data • DLL aligns DQ and DQS transitions with CK transitions. • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS • Burst lengths: 2, 4, or 8 • CAS Latency: 2, 2.5 • Auto Precharge option for each burst access • Auto Refresh and Self Refresh Modes • 7.8µs Maximum Average Periodic Refresh Interval • 2.5V (SSTL_2 compatible) I/O • VDDQ = 2.5V ± 0.2V • VDD = 2.5V ± 0.2V • Package : 66pin TSOP-II / 60 balls 0.8mmx1.0mm pitch CSP. Description The 256Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. It is internally configured as a quad-bank DRAM. The DDR SDRAM provides for programmable Read or Write burst lengths of 2, 4 or 8 locations. An Auto Precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. The 256Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double data rate As with standard SDRAMs, the pipelined, multibank architecarchitecture is essentially a 2n prefetch architecture with an ture of DDR SDRAMs allows for concurrent operation, interface designed to transfer two data words per clock cycle thereby providing high effective bandwidth by hiding row preDataSheet4U.com DataShee at the I/O pins. A single read or write access for the 256Mb charge and activation time. DDR SDRAM effectively consists of a single 2n-bit wide, one An auto refresh mode is provided along with a power-saving clock cycle data transfer at the internal DRAM core and two power-down mode. All inputs are compatible with the JEDEC corresponding n-bit wide, one-half-clock-cycle data transfers Standard for SSTL_2. All outputs are SSTL_2, Class II comat the I/O pins. patible. A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during Reads and by the memory controller during Writes. DQS is edgealigned with data for Reads and center-aligned with data for Writes. The 256Mb DDR SDRAM operates from a differential clock (CK and CK; the crossing of CK going high and CK going LOW is referred to as the positive edge of CK). Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address bits registered coincident with the Active command are used to select the bank and row to be accessed. The address bits registered coincident with the Read or Write command are used to select the bank and the starting column location for the burst access. Preliminary DataSheet4U.com 10/01 1 © NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. DataSheet 4 U .com www.DataSheet4U.com NT5DS64M4AT NT5DS64M4AW NT5DS32M8AT NT5DS32M8AW 256Mb DDR333/300 SDRAM Pin Configuration - 400mil TSOP II VDD NC VDDQ NC DQ0 VSSQ NC NC VDDQ NC DQ1 VSSQ NC NC VDDQ NC NC VDD NU NC WE CAS RAS CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD VDD DQ0 VDDQ NC DQ1 VSSQ NC DQ2 VDDQ NC DQ3 VSSQ NC NC VDDQ NC NC VDD NU NC WE CAS RAS CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 VSS DQ7 VSSQ NC DQ6 VDDQ NC DQ5 VSSQ NC DQ4 VDDQ NC NC VSSQ DQS NC VREF VSS DM* CK CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS VSS NC VSSQ NC DQ3 VDDQ NC NC VSSQ NC DQ2 VDDQ NC NC VSSQ DQS NC VREF VSS DM* CK CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS et4U.com DataSheet4U.com 23 24 25 26 27 28 29 30 31 32 33 DataShee 66-pin Plastic TSOP-II 400mil 32Mb x 8 NT5DS32M8AT 64Mb x 4 NT5DS64M4AT Column Address Table Organization 64Mb x 4 32Mb x 8 Column Address A0-A9, A11 A0-A9 *DM is internally loaded to match DQ and DQS identically. Preliminary DataSheet4U.com 10/01 2 © NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Pro.


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