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NT5DS64M4BF Dataheets PDF



Part Number NT5DS64M4BF
Manufacturers Nanya Techology
Logo Nanya Techology
Description (NT5DSxxMxBx) 256Mb DDR SDRAM
Datasheet NT5DS64M4BF DatasheetNT5DS64M4BF Datasheet (PDF)

www.DataSheet4U.com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Features CAS Latency and Frequency CAS Latency 3 2.5 Maximum Operating Frequency (MHz) DDR400B (-5T) 200 166 • • • • • • • • • • • • • • Double data rate architecture: two data transfers per clock cycle • Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at t.

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www.DataSheet4U.com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Features CAS Latency and Frequency CAS Latency 3 2.5 Maximum Operating Frequency (MHz) DDR400B (-5T) 200 166 • • • • • • • • • • • • • • Double data rate architecture: two data transfers per clock cycle • Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver • DQS is edge-aligned with data for reads and is centeraligned with data for writes • Differential clock inputs (CK and CK) Four internal banks for concurrent operation Data mask (DM) for write data DLL aligns DQ and DQS transitions with CK transitions Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS Burst lengths: 2, 4, or 8 CAS Latency: 2.5, 3 Auto Precharge option for each burst access Auto Refresh and Self Refresh Modes 7.8µs Maximum Average Periodic Refresh Interval SSTL_2 compatible I/O interface VDDQ = 2.6V ± 0.1V VDD = 2.6V ± 0.1V Lead-free and Halogen-free product available Description The 256Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. It is internally configured as a quad-bank DRAM. tion may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard SDRAMs, the pipelined, multibank architecThe 256Mb DDR SDRAM uses a double-data-rate architecture of DDR SDRAMs allows for concurrent operation, ture to achieve high-speed operation. The double data rate thereby providing high effective bandwidth by hiding row prearchitecture is essentially a 2n prefetch architecture with an charge and activation time. interface designed to transfer two data words per clock cycle DataSheet4U.com An auto refresh mode is provided along with a power-saving DataShee at the I/O pins. A single read or write access for the 256Mb Power Down mode. All inputs are compatible with the JEDEC DDR SDRAM effectively consists of a single 2n-bit wide, one Standard for SSTL_2. All outputs are SSTL_2, Class II comclock cycle data transfer at the internal DRAM core and two patible. corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins. The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS of operation. is a strobe transmitted by the DDR SDRAM during Reads and by the memory controller during Writes. DQS is edgealigned with data for Reads and center-aligned with data for Writes. The 256Mb DDR SDRAM operates from a differential clock (CK and CK; the crossing of CK going high and CK going LOW is referred to as the positive edge of CK). Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address bits registered coincident with the Active command are used to select the bank and row to be accessed. The address bits registered coincident with the Read or Write command are used to select the bank and the starting column location for the burst access. The DDR SDRAM provides for programmable Read or Write burst lengths of 2, 4, or 8 locations. An Auto Precharge func- REV 1.3 DataSheet4U.com 06/2003 1 © NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. DataSheet4 U .com www.DataSheet4U.com NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Pin Configuration - 400mil TSOP II (x4 / x8 / x16) VD D NC VDDQ NC DQ0 VSSQ NC NC VDDQ NC DQ1 VSSQ NC NC VDDQ NC NC VD D NU NC WE CAS RAS CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD VDD DQ0 VDDQ NC DQ1 V SSQ NC DQ2 VDDQ NC DQ3 VSSQ NC NC VDDQ NC NC VDD NU NC WE CAS RAS CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VD D VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDDQ LDQS NC VDD NU LDM* WE CAS RAS CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 V SS DQ15 V SSQ DQ14 DQ13 V DDQ DQ12 DQ11 V SSQ DQ10 DQ9 V DDQ DQ8 NC V SSQ UDQS NC V REF V SS UDM* CK CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 V SS VSS DQ7 VSSQ NC DQ6 VDDQ NC DQ5 VSSQ NC DQ4 VDDQ NC NC VSSQ DQS NC VREF VSS DM* CK CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4.


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