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NT5DS32M8CT Dataheets PDF



Part Number NT5DS32M8CT
Manufacturers Nanya Techology
Logo Nanya Techology
Description 256Mb SDRAM
Datasheet NT5DS32M8CT DatasheetNT5DS32M8CT Datasheet (PDF)

www.DataSheet4U.com NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS NT5DS16M16CG Features CAS Latency and Frequency CAS Latency 2 2.5 3 Maximum Operating Frequency (MHz) DDR400 DDR333 (5T) (6K/6KL) 133 166 166 200 - • • • • • • • • • • • • • • • DDR 256M bit, die C, based on 110nm design rules • Double data rate architecture: two data transfers per clock cycle • Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data a.

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www.DataSheet4U.com NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS NT5DS16M16CG Features CAS Latency and Frequency CAS Latency 2 2.5 3 Maximum Operating Frequency (MHz) DDR400 DDR333 (5T) (6K/6KL) 133 166 166 200 - • • • • • • • • • • • • • • • DDR 256M bit, die C, based on 110nm design rules • Double data rate architecture: two data transfers per clock cycle • Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver • DQS is edge-aligned with data for reads and is centeraligned with data for writes Differential clock inputs (CK and CK) Four internal banks for concurrent operation Data mask (DM) for write data DLL aligns DQ and DQS transitions with CK transitions Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS Burst lengths: 2, 4, or 8 CAS Latency: 2/2.5(DDR333) , 2.5/3(DDR400) Auto Precharge option for each burst access Auto Refresh and Self Refresh Modes 7.8ms Maximum Average Periodic Refresh Interval 2.5V (SSTL_2 compatible) I/O VDD = VDDQ = 2.5V ± 0.2V (DDR333) VDD = VDDQ = 2.6V ± 0.1V (DDR400) Available in Halogen and Lead Free packaging Description NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT, NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS, and NT5DS16M16CG are die C of 256Mb SDRAM devices based using DDR interface. They are all based on Nanya’s 110 nm design process. Read or Write command are used to select the bank and the starting column location for the burst access. The DDR SDRAM provides for programmable Read or Write burst lengths of 2, 4, or 8 locations. An Auto Precharge function may be enabled to provide a self-timed row precharge DataSheet4U.com DataShee The 256Mb DDR SDRAM uses a double-data-rate architecthat is initiated at the end of the burst access. ture to achieve high-speed operation. The double data rate As with standard SDRAMs, the pipelined, multibank architecarchitecture is essentially a 2n prefetch architecture with an ture of DDR SDRAMs allows for concurrent operation, interface designed to transfer two data words per clock cycle thereby providing high effective bandwidth by hiding row preat the I/O pins. A single read or write access for the 256Mb charge and activation time. DDR SDRAM effectively consists of a single 2n-bit wide, one clock cycle data transfer at the internal DRAM core and two An auto refresh mode is provided along with a power-saving corresponding n-bit wide, one-half-clock-cycle data transfers Power Down mode. All inputs are compatible with the JEDEC at the I/O pins. Standard for SSTL_2. All outputs are SSTL_2, Class II compatible. A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS The functionality described and the timing specifications is a strobe transmitted by the DDR SDRAM during Reads included in this data sheet are for the DLL Enabled mode of and by the memory controller during Writes. DQS is edgeoperation. aligned with data for Reads and center-aligned with data for Writes. The 256Mb DDR SDRAM operates from a differential clock (CK and CK; the crossing of CK going high and CK going LOW is referred to as the positive edge of CK). Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address bits registered coincident with the Active command are used to select the bank and row to be accessed. The address bits registered coincident with the REV 1.2 DataSheet4U.com Nov 10, 2005 1 © NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. DataSheet 4 U .com www.DataSheet4U.com NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS NT5DS16M16CG 256Mb DDR SDRAM Ordering Information Speed Org. Part Number NT5DS64M4CT-5T 64M x 4 NT5DS64M4CT-6K NT5DS32M8CT-5T 32M x 8 NT5DS32M8CT-6K/6KL NT5DS16M16CT-5T 16M x 16 NT5DS16M16CT-6K NT5DS64M4CS-5T 64M x 4 NT5DS64M4CS-6K NT5DS32M8CS-5T 32M x 8 NT5DS32M8CS-6K NT5DS16M16CS-5T 16M x 16 NT5DS16M16CS-6K NT5DS16M16CG-5T 16M x 16 NT5DS16M16CG-6K TSOP2 Green Packing Package Clock (MHz) CL-tRCD-tRP 200 TSOP2 166 200 TSOP2 166 200 TSOP2 166 200 166 200 166 200 166 200 166 2.5-3-3 3-3-3 2.5-3-3 3-3-3 2.5-3-3 3-3-3 2.5-3-3 3-3-3 2.5-3-3 2.5-3-3 3-3-3 2.5-3-3 3-3-3 3-3-3 Comments DDR400 DDR333 DDR400 DDR333 DDR400 DDR333 DDR400 DDR333 DDR400 DDR333 DDR400 DDR333 DDR400 DDR333 TSOP2 Green Packing TSOP2 Green Packing wBGA Green Package et4U.com Note: 1. At the present time, th.


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