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NT5DS32M16BG Dataheets PDF



Part Number NT5DS32M16BG
Manufacturers Nanya Techology
Logo Nanya Techology
Description (NT5DSxxMxBx) 512Mb DDR SDRAM
Datasheet NT5DS32M16BG DatasheetNT5DS32M16BG Datasheet (PDF)

www.DataSheet4U.com NT5DS128M4BF / NT5DS128M4BT/ NT5DS128M4BG (Green) / NT5DS128M4BS (Green) NT5DS64M8BF / NT5DS64M8BT/ NT5DS64M8BG (Green) / NT5DS64M8BS (Green) NT5DS32M16BF / NT5DS32M16BT / NT5DS32M16BG (Green) / NT5DS32M16BS (Green) 512Mb DDR SDRAM Features CAS Latency and Frequency CAS Latency 2 2.5 3 Maximum Operating Frequency (MHz) DDR400 DDR333 DDR266B (5T) (6K) (75B) 133 100 166 166 133 200 - • • • • • • • • • • • • • • DDR 512M bit, die B, based on 110nm design rules • Double data .

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www.DataSheet4U.com NT5DS128M4BF / NT5DS128M4BT/ NT5DS128M4BG (Green) / NT5DS128M4BS (Green) NT5DS64M8BF / NT5DS64M8BT/ NT5DS64M8BG (Green) / NT5DS64M8BS (Green) NT5DS32M16BF / NT5DS32M16BT / NT5DS32M16BG (Green) / NT5DS32M16BS (Green) 512Mb DDR SDRAM Features CAS Latency and Frequency CAS Latency 2 2.5 3 Maximum Operating Frequency (MHz) DDR400 DDR333 DDR266B (5T) (6K) (75B) 133 100 166 166 133 200 - • • • • • • • • • • • • • • DDR 512M bit, die B, based on 110nm design rules • Double data rate architecture: two data transfers per clock cycle • Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver • DQS is edge-aligned with data for reads and is centeraligned with data for writes Differential clock inputs (CK and CK) Four internal banks for concurrent operation Data mask (DM) for write data DLL aligns DQ and DQS transitions with CK transitions Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS Burst lengths: 2, 4, or 8 CAS Latency: 2 / 2.5 (6K & 75B), 2.5 / 3 (5T) Auto Precharge option for each burst access Auto Refresh and Self Refresh Modes 7.8µs Maximum Average Periodic Refresh Interval 2.5V (SSTL_2 compatible) I/O VDD = VDDQ = 2.5V ± 0.2V (6K & 75B) VDD = VDDQ = 2.6V ± 0.1V (5T) Description NT5DS128M4BF, NT5DS128M4BT, NT5DS64M8BF, NT5DS64M8BT, NT5DS32M16BF and NT5DS32M16BT are die B of 512Mb SDRAM devices based using DDR interface. They are all based on Nanya’s 110 nm design process. accessed. The address bits registered coincident with the Read or Write command are used to select the bank and the starting column location for the burst access. The DDR SDRAM provides for programmable Read or Write The 512Mb DDR SDRAM is a high-speed CMOS, dynamic burst lengths of 2, 4, or 8 locations. An Auto Precharge funcrandom-access memory containing 536,870,912 bits. It is tion may be enabled to provide a self-timed row precharge DataSheet4U.com e internally configured as a quad-bank DRAM. that is initiated at the end of the burst access. DataShe The 512Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 512Mb DDR SDRAM effectively consists of a single 2n-bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins. A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during Reads and by the memory controller during Writes. DQS is edgealigned with data for Reads and center-aligned with data for Writes. The 512Mb DDR SDRAM operates from a differential clock (CK and CK; the crossing of CK going high and CK going LOW is referred to as the positive edge of CK). Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address bits registered coincident with the Active command are used to select the bank and row to be As with standard SDRAMs, the pipelined, multibank architecture of DDR SDRAMs allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time. An auto refresh mode is provided along with a power-saving Power Down mode. All inputs are compatible with the JEDEC Standard for SSTL_2. All outputs are SSTL_2, Class II compatible. The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation. REV 1.3 DataSheet4U.com 15 Feb 2006 1 © NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. DataSheet 4 U .com www.DataSheet4U.com NT5DS128M4BF / NT5DS128M4BT / NT5DS128M4BG (Green) / NT5DS128M4BS (Green) NT5DS64M8BF / NT5DS64M8BT / NT5DS64M8BG (Green) / NT5DS64M8BS (Green) NT5DS32M16BF / NT5DS32M16BT / NT5DS32M16BG (Green) / NT5DS32M16BS (Green) 512Mb DDR SDRAM Ordering Information (Non-Green) Speed Org. Part Number NT5DS128M4BT-5T NT5DS128M4BT-6K NT5DS128M4BT-75B 128M x 4 NT5DS128M4BF-5T NT5DS128M4BF-6K NT5DS128M4BF-75B NT5DS64M8BT-5T NT5DS64M8BT-6K NT5DS64M8BT-75B 64M x 8 NT5DS64M8BF-5T NT5DS64M8BF-6K NT5DS64M8BF-75B NT5DS32M16BT-5T NT5DS32M16BT-6K NT5DS32M16BT-75B 32M x 16 NT5DS32M16BF-5T NT5DS32M16BF-6K NT5DS32M16BF-75B 60ball BGA 0.8m.


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