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NT5DS16M8AT Dataheets PDF



Part Number NT5DS16M8AT
Manufacturers Nanya Techology
Logo Nanya Techology
Description (NT5DS16M8AT / NT5DS32M4AT) 128Mb DDR SDRAM
Datasheet NT5DS16M8AT DatasheetNT5DS16M8AT Datasheet (PDF)

www.DataSheet4U.com NT5DS32M4AT NT5DS16M8AT 128Mb Double Data Rate SDRAM Features CAS Latency and Frequency Maximum Operating Frequency (MHz)* DDR266A DDR266B DDR200 (-7K) (-75B) (-8B) 2 133 100 100 2.5 143 133 125 * Values are nominal (exact tCK should be used). CAS Latency • Double data rate architecture: two data transfers per clock cycle • Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver • DQS is edge-aligned with data for.

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www.DataSheet4U.com NT5DS32M4AT NT5DS16M8AT 128Mb Double Data Rate SDRAM Features CAS Latency and Frequency Maximum Operating Frequency (MHz)* DDR266A DDR266B DDR200 (-7K) (-75B) (-8B) 2 133 100 100 2.5 143 133 125 * Values are nominal (exact tCK should be used). CAS Latency • Double data rate architecture: two data transfers per clock cycle • Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver • DQS is edge-aligned with data for reads and is centeraligned with data for writes • Differential clock inputs (CK and CK) • Four internal banks for concurrent operation • Data mask (DM) for write data • DLL aligns DQ and DQS transitions with CK transitions, also aligns QFC transitions with CK during Read cycles • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS • Burst lengths: 2, 4, or 8 • CAS Latency: 2, 2.5 • Auto Precharge option for each burst access • Auto Refresh and Self Refresh Modes • 15.6 µs Maximum Average Periodic Refresh Interval • Supports t RAS lockout feature • 2.5V (SSTL_2 compatible) I/O • VDDQ = 2.5V ± 0.2V • VDD = 2.5V ± 0.2V • -7K parts support PC2100 modules. -75B parts support PC2100 modules -8B parts support PC1600 modules Description The 128Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 134,217,728 bits. It is internally configured as a quad-bank DRAM. Read or Write command are used to select the bank and the starting column location for the burst access. The DDR SDRAM provides for programmable Read or Write The 128Mb DDR SDRAM uses a double-data-rate architecburst lengths of 2, 4 or 8 locations. An Auto Precharge funcDataSheet4U.com DataShee ture to achieve high-speed operation. The double data rate tion may be enabled to provide a self-timed row precharge architecture is essentially a 2n prefetch architecture with an that is initiated at the end of the burst access. interface designed to transfer two data words per clock cycle As with standard SDRAMs, the pipelined, multibank architecat the I/O pins. A single read or write access for the 128Mb ture of DDR SDRAMs allows for concurrent operation, DDR SDRAM effectively consists of a single 2n-bit wide, one thereby providing high effective bandwidth by hiding row preclock cycle data transfer at the internal DRAM core and two charge and activation time. corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins. An auto refresh mode is provided along with a power-saving power-down mode. All inputs are compatible with the JEDEC A bidirectional data strobe (DQS) is transmitted externally, Standard for SSTL_2. All outputs are SSTL_2, Class II comalong with data, for use in data capture at the receiver. DQS patible. is a strobe transmitted by the DDR SDRAM during Reads and by the memory controller during Writes. DQS is edgeNote: The functionality described and the timing specifialigned with data for Reads and center-aligned with data for cations included in this data sheet are for the DLL Writes. Enabled mode of operation. The 128Mb DDR SDRAM operates from a differential clock (CK and CK; the crossing of CK going high and CK going LOW is referred to as the positive edge of CK). Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address bits registered coincident with the Active command are used to select the bank and row to be accessed. The address bits registered coincident with the REV 1.0 DataSheet4U.com May, 2001 1 © NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. DataSheet4 U .com www.DataSheet4U.com NT5DS32M4AT NT5DS16M8AT 128Mb Double Data Rate SDRAM Pin Configuration - 128Mb DDR SDRAM (x4 / x8) VD D NC VDDQ NC DQ0 VSSQ NC NC VDDQ NC DQ1 VSSQ NC NC VDDQ NC NC VD D DNU, QFC + NC WE CAS RAS CS NC BA0 BA1 A10/AP A0 A1 A2 A3 V DD V DD DQ0 VDDQ NC DQ1 V SSQ NC DQ2 VDDQ NC DQ3 VSSQ NC NC VDDQ NC NC VDD DNU, QFC+ NC WE CAS RAS CS NC BA0 BA1 A10/AP A0 A1 A2 A3 V DD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 VSS DQ7 VSSQ NC DQ6 VDDQ NC DQ5 VSSQ NC DQ4 VDDQ NC NC VSSQ DQS NC VREF VSS DM* CK CK CKE NC NC A11 A9 A8 A7 A6 A5 A4 VSS VSS NC VSSQ NC DQ3 VDDQ NC NC VSSQ NC DQ2 VDDQ NC NC VSSQ DQS NC VREF VSS DM* CK CK CKE NC NC A11 A9 A8 A7 A6 A5 A4 VSS et4U.com DataSheet4U.com 44 43 42 41 40 39 38 37 36 35 34 DataShee 66-pin Plastic TSOP-II.


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