NT5DS16M8AW

www.DataSheet4U.com NT5DS32M4AT NT5DS32M4AW NT5DS16M8AT NT5DS16M8AW 128Mb DDR333/300 SDRAM Features CAS Latency and Frequency Maximum Operating Frequency (MHz)* DDR333 DDR300 (-6) (-66) 2 133 133 2.5 166 150 * Values are nominal (exact tCK should be used). CAS Latency Double data rate architecture: two data transfers per clock cycle Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver DQS is edge-aligned with data for reads and is centeraligned with data for writes Differential clock inputs (CK and CK) Four internal banks for concurrent operation Data mask (DM) for write data DLL aligns DQ and DQS transitions with CK transitions, also aligns QFC transitions with CK during Read cycles Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS Burst lengths: 2, 4, or 8 CAS Latency: 2, 2.5 Auto Precharge option for each burst access Auto Refresh and Self Refresh Modes 15.6µs Maximum Average Periodic Refresh Interval 2.5V (SSTL_2 compatible) I/O VDDQ = 2.5V ± 0.2V VDD = 2.5V ± 0.2V For -6 speed grade : Support PC2700 modules. For -66 speed grade : Support PC2400 modules Package : - 66pin TSOP-II - 60ball 0.8mmx1.0mm pitch CSP Description The 128Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 134,217,728 bits. It is internally configured as a quad-bank DRAM. Read or Write command are used to select the bank and the ...