HY5DU56822LT

www.DataSheet4U.com HY5DU56422A(L)T HY5DU56822A(L)T HY5DU561622A(L)T 256M-S DDR SDRAM HY5DU56422A(L)T HY5DU56822A(L)T HY5DU561622A(L)T DataSheet4U.com DataShee This document is a general product description and is subject to change without notice. Hynix semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.4/ May. 02 DataSheet4U.com www.DataSheet4U.com HY5DU56422A(L)T HY5DU56822A(L)T HY5DU561622A(L)T Revision History 1. Revision 0.2 (Jan. 02) 1) Define Preliminary Specification 2. Revision 0.3 (Mar. 02) 1) Define IDD Specification 2) Added programmable Cas Latrency 1.5 3) Changed VREF value from min (0.49*VDDQ) & max (0.51*VDDQ) to min (VDDQ/2-50mV) & max (VDDQ/2+50mV) 4) Changed ILI (Input Leakage Current) value from +/- 5uA to +/- 2uA 3. Revision 0.4 (May. 02) 1) Added comment of Cas Latrency 1.5 & 3 et4U.com DataSheet4U.com DataShee Rev. 0.4/ May. 02 2 DataSheet4U.com www.DataSheet4U.com HY5DU56422A(L)T HY5DU56822A(L)T HY5DU561622A(L)T DESCRIPTION PRELIMINARY The Hynix HY5DU56422, HY5DU56822 and HY5DU561622 are a 268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. The Hynix 256Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of ...