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3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH 128 x 128
FEATURES:
• • • • • • • • • • •
IDT72V8988
128 x 128 channel non-blocking switch Automatic signal identification (ST-BUS®, GCI) 4 RX inputs—32 channels at 64 Kbit/s per serial line 4 TX outputs—32 channels at 64 Kbit/s per serial line Three-state serial outputs Microprocessor Interface (8-bit data bus) Frame Integrity for data applications 3.3V Power Supply Available in 44-pin Plastic Leaded Chip Carrier (PLCC), and 44-pin Plastic Quad Flatpack (PQFP) Operating Temperature Range -40°C to +85°C 3.3V I/O with 5V Tolerant Inputs
per-channel variable or constant throughput delay modes and microprocessor read and write access to individual channels. As an important function of a digital switch is to maintain sequence integrity and minimize throughput delay, the IDT72V8988 is an ideal solution for most switching needs.
FUNCTIONAL DESCRIPTION
Frame sequence, constant throughput delay, and guaranteed minimum delay are high priority requirements in today’s integrated data and multimedia networks. The IDT72V8988 provides these functions on a per-channel basis using a standard microprocessor control interface. Each of the four serial lines is designed to switch 64 Kbit/s PCM or N x 64 Kbit/s data. In Processor Mode, the microprocessor can access the input and output time slots to control other devices such as ISDN transceivers and trunk interfaces. Supporting both GCI and ST-BUS® formats, IDT72V8988 has incorporated an internal circuit to automatically identify the polarity and format of the frame synchronization. A functional block diagram of the IDT72V8988 device is shown on page 1. The serial streams operate continuously at 2.048 Mb/s and are arranged in 125µs wide frames each containing 32, 8-bit channels. Four input (RX0-3) and
DESCRIPTION:
The IDT72V8988 is an ST-BUS®/GCI compatible digital switch controlled by a microprocessor. The IDT72V8988 can handle as many as 128, 64 Kbit/s input and output channels. Those 128 channels are divided into 4 serial inputs and outputs, each of which consists of 32 channels. The IDT72V8988 provides
FUNCTIONAL BLOCK DIAGRAM
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C4i
F0i
VCC
GND
ODE
Timing Unit
RX0 RX1 RX2 RX3
Output MUX
TX0
Receive Serial Data Streams
Data Memory Control Register Connection Memory
Transmit Serial Data Streams
TX1 TX2 TX3
Microprocessor Interface
5704 drw01
DS CS R/W A0/ DTA D0/ A5 D7
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IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The ST-BUS is a trademark of Mitel Corp.
AUGUST 2003
DSC-5704/5
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
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IDT72V8988 3.3V Time Slot Interchange Digital Switch 128 x 128
Commercial Temperature Range
PIN CONFIGURATION
DNC(1) DNC(1) DTA
INDEX
6
5
4
3
2
44
43
42
41
RX3 VCC VCC VCC VCC VCC F0i C4i A0 A1 A2
1
40
DNC(1)
RX2
RX1
RX0
ODE
TX0
TX1
TX2
7 8 9 10 11 12 13 14 15 16 17
39 38 37 36 35 34 33 32 31 30 29
TX3 DNC(1) DNC(1) DNC(1) DNC(1) GND D0 D1 D2 D3 D4
18
19
20
21
22
23
24
25
26
27
A3
A4
A5
D7
D6
DNC(1)
D5
DNC(1)
DS
R/W
CS
28
5704 drw02
PLCC: 0.05in. pitch, 0.65in. x 0.65in (J44-1, order code: J) TOP VIEW
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DataShee
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DTA DNC(1)
DNC(1)
INDEX
44
43
42
41
40
39
38
37
36
35
RX3 VCC VCC VCC VCC VCC F0i C4i A0 A1 A2
34
DNC(1)
ODE TX0
RX2
RX1
RX0
TX1
TX2
1 2 3 4 5 6 7 8 9 10 11
33 32 31 30 29 28 27 26 25 24 23
TX3 DNC(1) DNC(1) DNC(1) DNC(1) GND D0 D1 D2 D3 D4
12
13
14
15
16
17
18
19
20
21
22
5704 drw03
A3
A4
A5
CS D7
D6
DNC(1)
D5
PQFP: 0.80mm pitch, 10mm x 10mm (DB44-1, order code: DB) TOP VIEW
NOTES:
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2
DNC(1)
DS R/W
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IDT72V8988 3.3V Time Slot Interchange Digital Switch 128 x 128
Commercial Temperature Range
PIN DESCRIPTIONS
SYMBOL
GND VCC
NAME
Ground. VCC Data Acknowledgment (Open Drain) RX Input 0 to 3 Frame Pulse Clock Address 0 to 5 Data Strobe Read/Write Chip Select Data Bus 0 to 7 TX Outputs 0 to 3 (Three-state Outputs) Output Drive Enable
I/O
DESCRIPTION
Ground Rail. +3.3 Volt Power Supply. This active LOW output indicates that a data bus transfer is complete. A pull-up resistor is required at this output. Serial data input streams. These streams have 32 channels at data rates of 2.048 Mb/s. This input accepts and automatically identifies frame synchronization signals formatted according to different backplane specifications such as ST-BUS® and GCI. 4.096 MHz serial clock for shifting data in and out of the data streams. These lines provide the address to IDT72V8988 internal registers. This is the input for the active HIGH data strobe on the microprocessor interface. This input operates with CS to enable the internal read and write generation. This input controls the direction of the data bus lines (D0-D7) during a.