Document
MC74LVXT4051
Analog Multiplexer/ Demultiplexer
High−Performance Silicon−Gate CMOS
The MC74LVXT4051 utilizes silicon−gate CMOS technology to achieve fast propagation delays, low ON resistances, and low leakage currents. This analog multiplexer/demultiplexer controls analog voltages that may vary across the complete power supply range (from VCC to VEE).
The LVXT4051 is similar in pinout to the LVX8051, the HC4051A, and the metal−gate MC14051B. The Channel−Select inputs determine which one of the Analog Inputs/Outputs is to be connected, by means of an analog switch, to the Common Output/Input. When the Enable pin is HIGH, all analog switches are turned off.
The Channel−Select and Enable inputs are compatible with standard TTL levels. These inputs are over−voltage tolerant (OVT) for level translation from 6.0 V down to 3.0 V.
This device has been designed so the ON resistance (RON) is more linear over input voltage than the RON of metal−gate CMOS analog switches and High−Speed CMOS analog switches.
Features
• Select Pins Compatible with TTL Levels • Fast Switching and Propagation Speeds • Low Crosstalk Between Switches • Analog Power Supply Range (VCC − VEE) = *3.0 V to )3.0 V • Digital (Control) Power Supply Range (VCC − GND) = 2.5 to 6.0 V • Improved Linearity and Lower ON Resistance Than Metal−Gate,
HSL, or VHC Counterparts
• Low Noise • Designed to Operate on a Single Supply with VEE = GND, or Using
Split Supplies up to ±3.0 V
• Break−Before−Make Circuitry • These Devices are Pb−Free and are RoHS Compliant
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SOIC−16 D SUFFIX CASE 751B
TSSOP−16 DT SUFFIX CASE 948F
PIN ASSIGNMENT
VCC X2 X1 X0 X3 A B C 16 15 14 13 12 11 10 9
123 456 78 X4 X6 X X7 X5 Enable VEE GND
MARKING DIAGRAMS
16 LVXT4051G AWLYWW
1 SOIC−16
16 LVXT 4051 ALYWG G
1
TSSOP−16
LVXT4051 = Specific Device Code
A
= Assembly Location
WL, L
= Wafer Lot
Y
= Year
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
1
August, 2014 − Rev. 6
Publication Order Number: MC74LVXT4051/D
MC74LVXT4051
FUNCTION TABLE
Control Inputs
Enable
Select CBA
L
LLL
L
L LH
L
LHL
L
L HH
L
HL L
L
HLH
L
HH L
L
HHH
H
XXX
X = Don’t Care
ON Channels
X0 X1 X2 X3 X4 X5 X6 X7 NONE
X0 13 X1 14
X2 15
ANALOG INPUTS/OUTPUTS
X3 12 X4 1
5 X5
X6 2
X7 4
A 11
CHANNEL SELECT INPUTS
10 B C9
ENABLE 6
MULTIPLEXER/ DEMULTIPLEXER
3
X
COMMON OUTPUT/INPUT
PIN 16 = VCC PIN 8 = GND
PIN 7 = VEE
Figure 1. Logic Diagram Single−Pole, 8−Position Plus Common Off
ORDERING INFORMATION Device
Package
Shipping†
MC74LVXT4051DG
SOIC−16 (Pb−Free)
48 Units / Rail
MC74LVXT4051DR2G
SOIC−16 (Pb−Free)
2500 Tape & Reel
MC74LVXT4051DTG
TSSOP−16 (Pb−Free)
96 Units / Rail
MC74LVXT4051DTR2G
TSSOP−16 (Pb−Free)
2500 Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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MC74LVXT4051
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
VEE
Negative DC Supply Voltage
VCC
Positive DC Supply Voltage
VIS
Analog Input Voltage
VIN
Digital Input Voltage
I
DC Current, Into or Out of Any Pin
(Referenced to GND)
−7.0 to +0.5
V
(Referenced to GND)
−0.5 to +7.0
V
(Referenced to VEE)
−0.5 to +7.0
VEE − 0.5 to VCC + 0.5
V
(Referenced to GND)
−0.5 to 7.0
V
±20
mA
TSTG TL TJ qJA
Storage Temperature Range Lead Temperature, 1 mm from Case for 10 Seconds Junction Temperature under Bias Thermal Resistance
SOIC TSSOP
−65 to +150 260 +150
143 164
_C _C _C °C/W
PD
Power Dissipation in Still Air,
SOIC
500
mW
TSSOP
450
MSL
Moisture Sensitivity
Level 1
FR VESD
Flammability Rating ESD Withstand Voltage
Oxygen Index: 30% − 35% UL 94−V0 @ 0.125 in
Human Body Model (Note 1)
u2000
V
Machine Model (Note 2)
u200
Charged Device Model (Note 3)
u1000
ILATCHUP Latchup Performance
Above VCC and Below GND at 125°C (Note 4)
±300
mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Tested to EIA/JESD22−A114−A. 2. Tested to EIA/JESD22−A115−A. 3. Tested to JESD22−C101−A. 4. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
VEE
Negative DC Supply Voltage
(Referenced to GND) −6.0
GND
V
VCC
Positive DC Supply Voltage
(Referenced to GND)
2.5
(Referenced to VEE)
2.5
6.0
V
6.0
VIS
Analog Input Voltage
VEE
VCC
V
VIN
Digital Input Voltage
(Note 5) (Referenced to GND)
0
6.0
V
TA
Operating Temperature Range, All Package Ty.