Swipeater Controller. AX88872P Datasheet

AX88872P Controller. Datasheet pdf. Equivalent

Part AX88872P
Description 10/100BASE Dual Speed Swipeater Controller
Feature www.DataSheet4U.com AX88872P 10/100BASE Dual Speed “Swipeater” Controller 10/100BASE Dual Speed 8-P.
Manufacture ASIX Electronics Corporation
Datasheet
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AX88872P
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AX88872P
10/100BASE Dual Speed “Swipeater” Controller
10/100BASE Dual Speed 8-Port Repeater with 4-Port Switch
Document No.: AX872-13 / V1.3 / Aug. 11 ’99
Features
Support 8 10/100Mbps RMII I/F repeater ports and
2 10/100Mbps RMII/MII switch ports
IEEE 802.3u repeater compatible
Support virtual switch mode and Master/Slave
mode for the cascade application
Build in 4-ports 10/100Mbps Switch engine with
following features
ü Low cost SSRAM interface to reduce system cost
ü One or two 64K*32bit SSRAM to buffer packets
ü 4/8 K MAC Address Entry Table is supported
ü Auto learning and filtering
ü Aging the MAC Address table is supported
optionally
ü Three forwarding modes are supported : Store-
and-Forward, Fragment-Free and Auto-Forward
ü Flow-control is supported optionally.
ü 802.3x flow control is supported in full duplex
mode
ü Back-pressure base flow control is supported in
half duplex mode
ü Ext. Buffer Memory auto testing
ü Routing and Learning at wire speed (148800
packets/sec at 100Mbps)
Up-to 4 repeaters can be cascaded for vertical
expansion
Up-to 3 chips can be cascaded locally for horizontal
expansion
All ports can be separately isolated or partitioned in
response to fault condition
Separate jabber and partition state machines for
each port
Per-port LED display for Jabber, Partition,
Activity. RAM test fail and collision, buffer
utilization (%) and global traffic utilization (%) for
10/100Mbps presentation
Power on LED diagnosis. All the LED display will
follow the “ON-OFF-ON-OFF-Normal” operation
procedure during/after power on reset
50MHz Operation, 3.3volt and 208-pin PQFP
Product description
The AX88872 10/100Mbps Dual Speed “Swipeater” Controller is “a dual speed repeater with build in 4-ports
switch function” It is design for low cost dumb HUB application. The AX88872 directly supports up-to eight
10/100Mbps automatic links RMII interfaces. Maximum up-to 96 repeater ports can be constructed by stacking 1
AX88872 and 2 AX88873 chips horizontally and then cascading 4 horizontal boards vertically. About the build in
4-port switch: The switch port3 is fixed to 10Mbps speed and connects to 10Mbps repeater segment, The switch port2
is fixed to 100Mbps and connects to 100M repeater segment. The switch ports 0 and 1 are connected to external MII
or RMII interfaces for various applications. For example, one port is used for down link and the other is used for up
link to extend the network topology. The other case is one port for up link and the other port for server. The AX88872
is designed base on IEEE 802.3u clause 27 “ Repeater for 100Mb/s base-band networks” It is fully compatible with
IEEE 802.3u standard. Please refer Ax873-12.doc to get more information about AX88873.
System Block Diagram
10Mbps and 100Mbps Vertical cascade up to 4 stacks
Buffer
AX88873 #1
Repeater Controller
10Mbps horizontal cascade
100Mbps horizontal cascade
AX88873 #0
Repeater Controller
AX88872 #0
Swipeater Controller
PHY for Up-link
2 Quad RMII PHY
2 Quad RMII PHY
2 Quad RMII PHY
PHY for Down-link or Server
Always contact ASIX for possible updates before starting a design.
This data sheet contains new products information. ASIX ELECTRONICS reserves the rights to modify the product specification without notice. No
liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
ASIX ELECTRONICS CORPORATION
First Released Date : APR/09/1999
2F, NO.13, Industry East Rd. II, Science-based Industrial Park, Hsin-Chu City, Taiwan, R.O.C.
TEL: 886-3-579-9500
FAX: 886-3-579-9558
http://www.asix.com.tw
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AX88872P
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AX88872P Swipeater Controller
CONTENTS
CONFIDENTIAL
PRELIMINARY
1.0 AX88872 OVERVIEW ....................................................................................................................................... 4
1.1 GENERAL DESCRIPTION...................................................................................................................................... 4
1.2 AX88872 BLOCK DIAGRAM: .............................................................................................................................. 5
1.3 PIN CONNECTION DIAGRAM ............................................................................................................................... 6
2.0 PIN DESCRIPTION ........................................................................................................................................... 7
2.1 RMII INTERFACE FOR REPEATER PORTS............................................................................................................... 7
2.1.1 Repeater Port 0.......................................................................................................................................... 7
2.1.2 Repeater Port 1.......................................................................................................................................... 7
2.1.3 Repeater Port 2.......................................................................................................................................... 8
2.1.4 Repeater Port 3.......................................................................................................................................... 8
2.1.5 Repeater Port 4.......................................................................................................................................... 8
2.1.6 Repeater Port 5.......................................................................................................................................... 8
2.1.7 Repeater Port 6.......................................................................................................................................... 9
2.1.8 Repeater Port 7.......................................................................................................................................... 9
2.2 MII/RMII INTERFACE FOR SWITCH PORTS ........................................................................................................... 9
2.2.1 Switch Port 0.............................................................................................................................................. 9
2.2.2 Switch Port 1............................................................................................................................................ 10
2.3 EXPANSION BUS INTERFACE FOR 100 MBPS....................................................................................................... 11
2.4 EXPANSION BUS INTERFACE FOR 10 MBPS......................................................................................................... 11
2.5 LED DISPLAY.................................................................................................................................................. 12
2.6 BUFFER MEMORY PINS GROUP ........................................................................................................................... 13
2.7 MISCELLANEOUS.............................................................................................................................................. 14
2.8 POWER ON CONFIGURATION SETUP SIGNALS CROSS REFERENCE TABLE ................................................................ 15
3.0 FUNCTIONAL DESCRIPTION ...................................................................................................................... 18
3.1 REPEATER STATE MACHINE.............................................................................................................................. 18
3.2 RXE /TXE CONTROL ...................................................................................................................................... 18
3.3 JABBER STATE MACHINE.................................................................................................................................. 18
3.4 PARTITION STATE MACHINE............................................................................................................................. 18
3.5 OPERATION OF THE BUILT-IN SWITCH............................................................................................................... 19
3.5.1 Packet Filtering and Forwarding Process ................................................................................................ 19
3.5.2 MAC Address Learning and Aging Process .............................................................................................. 19
3.5.3 Flow Control Process............................................................................................................................... 19
3.6 LED DISPLAY INTERFACE ................................................................................................................................ 20
4.0 INTERNAL REGISTERS ................................................................................................................................ 22
5.0 ELECTRICAL SPECIFICATION AND TIMING.......................................................................................... 23
5.1 ABSOLUTE MAXIMUM RATINGS ........................................................................................................................ 23
5.2 GENERAL OPERATION CONDITIONS................................................................................................................... 23
5.3 DC CHARACTERISTICS..................................................................................................................................... 23
5.4 AC SPECIFICATIONS ......................................................................................................................................... 24
5.4.1 LCLK ....................................................................................................................................................... 24
5.4.2 Reset Timing ............................................................................................................................................ 24
5.4.3 RMII Interface Timing TX & RX............................................................................................................... 25
5.4.4 MII Interface Timing TX & RX................................................................................................................. 26
5.4.5 SRAM read cycle...................................................................................................................................... 27
5.4.6 SRAM write cycle..................................................................................................................................... 28
5.4.7 LED DISPLAY ......................................................................................................................................... 29
5.4.8 LED Display after Reset........................................................................................................................... 29
2 ASIX ELECTRONICS CORPORATION
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