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CY7C1357B Dataheets PDF



Part Number CY7C1357B
Manufacturers Cypress Semiconductor
Logo Cypress Semiconductor
Description (CY7C1355B / CY7C1357B) 9-Mb (256K x 36/512K x 18) Flow-Through SRAM
Datasheet CY7C1357B DatasheetCY7C1357B Datasheet (PDF)

www.DataSheet4U.com CY7C1355B CY7C1357B 9-Mb (256K x 36/512K x 18) Flow-Through SRAM with NoBL™ Architecture Features • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles. • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through operation.

  CY7C1357B   CY7C1357B


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www.DataSheet4U.com CY7C1355B CY7C1357B 9-Mb (256K x 36/512K x 18) Flow-Through SRAM with NoBL™ Architecture Features • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles. • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through operation • Byte Write capability • 3.3V/2.5V I/O power supply • Fast clock-to-output times — 6.5 ns (for 133-MHz device) — 7.0 ns (for 117-MHz device) — 7.5 ns (for 100-MHz device) • Clock Enable (CEN) pin to enable clock and suspend operation • Synchronous self-timed writes • Asynchronous Output Enable • Offered in JEDEC-standard 100 TQFP, 119-Ball BGA and 165-Ball fBGA packages • Three chip enables for simple depth expansion. • Automatic Power-down feature available using ZZ mode or CE deselect. • JTAG boundary scan for BGA and fBGA packages • Burst Capability—linear or interleaved burst order • Low standby power Functional Description[1] The CY7C1355B/CY7C1357B is a 3.3V, 256K x 36/ 512K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1355B/CY7C1357B is equipped with the advanced No Bus Latency (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent Write-Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is 6.5 ns (133-MHz device). Write operations are controlled by the two or four Byte Write Select (BWX) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. In order to avoid bus contention, the output drivers are synchronously three-stated during the data portion of a write sequence. Selection Guide 133 MHz Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 6.5 250 30 117 MHz 7.0 220 30 100 MHz 7.5 180 30 Unit ns mA mA Note: 1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05117 Rev. *B • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised January 27, 2004 DataSheet 4 U .com www.DataSheet4U.com CY7C1355B CY7C1357B 1 Logic Block Diagram – CY7C1355B (256K x 36) A0, A1, A MODE CLK CEN C CE ADV/LD C WRITE ADDRESS REGISTER ADDRESS REGISTER A1 D1 A0 D0 Q1 A1' A0' Q0 BURST LOGIC ADV/LD BWA BWA1, B A0, A BWC WRITE REGISTRY ADDRESS AND DATA COHERENCY CONTROL LOGIC A1 REGISTER WRITE DRIVERS MEMORY ARRAY S E N S E A M P S D A T A S T E E R I N G O U T P U T B U F F E R S E MODE BW D CLK CEN WEC A0 CE ADV/LD C WRITE ADDRESS REGISTER D1 D0 BURST LOGIC Q1 A1' A0' Q0 DQs DQPA DQPB DQPC DQPD OE CE1 CE2 CE3 ZZ INPUT E REGISTER READ LOGIC ADV/LD BWA 2 SLEEP CONTROL BWB Logic Block Diagram – CY7C1357B (512K x 18) WE A0, A1, A MODE CLK CEN C CE ADV/LD C WRITE ADDRESS READ LOGIC REGISTER ADDRESS REGISTER A1 D1 A0 D0 Q1 A1' A0' Q0 WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC WRITE DRIVERS MEMORY ARRAY S E N S E A M P S D A T A S T E E R I N G O U T P U T B U F F E R S E DQs DQPA DQPB BURST LOGIC OE CE1 CE2 CE3 ZZ INPUT E REGISTER O U T P U T B U F F E R S E SLEEP CONTROL ADV/LD BWA BWB WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC WRITE DRIVERS MEMORY ARRAY S E N S E A M P S D A T A S T E E R I N G DQs DQPA DQPB WE OE CE1 CE2 CE3 ZZ INPUT E REGISTER READ LOGIC SLEEP CONTROL Document #: 38-05117 Rev. *B Page 2 of 33 DataSheet 4 U .com www.DataSheet4U.com CY7C1355B CY7C1357B Pin Configurations 100-lead TQFP BWB BWA CE1 CE2 CE3 VDD VSS NC / 18M BWD BWC CEN CLK ADV/LD WE OE A 82 100 A 99 A 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 A BYTE C BYTE D DQPC DQC DQC VDDQ VSS DQC DQC DQC DQC VSS VDDQ DQC DQC Vss/DNU VDD NC VSS DQD DQD VDDQ VSS DQD DQD DQD DQD VSS VDDQ DQD DQD DQPD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 81 A CY7C1355B 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 43 44 45 46 47 48 49 50 DQPB DQB DQB VDDQ VSS DQB DQB DQB DQB VSS VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA DQA DQA VSS VDDQ DQA DQA DQPA BYTE B BYTE A 39 .


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