CY7C1347B

www.DataSheet4U.com 1CY7C1347 CY7C1347B 128K x 36 Synchronous-Pipelined Cache RAM Features Supports 100-MHz bus for Pentium and PowerPC™ operations with zero wait states Fully registered inputs and outputs for pipelined operation 128K by 36 common I/O architecture 3.3V core power supply 2.5V/3.3V I/O operation Fast clock-to-output times — 3.5 ns (for 166-MHz device) — 4.0 ns (for 133-MHz device) — 5.5 ns (for 100-MHz device) User-selectable burst counter supporting Intel Pentium interleaved or linear burst sequences Separate processor and controller address strobes Synchronous self-timed writes Asynchronous output enable JEDEC-standard 100 TQFP pinout “ZZ” Sleep Mode option and Stop Clock option Available in Industrial and Commercial Temperature ranges The CY7C1347B I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise is 3.5 ns (166-MHz device). The CY7C1347B supports either the interleaved burst sequence used by the Intel Pentium processor or a linear burst sequence used by processors such as the PowerPC. The burst sequence is selected through the MODE pin. Accesses can be initiated by asserting either the Processor Address Strobe (ADSP) or the Controller Address Stro...